forked from Minki/linux
67dc320d47
This patch moves 4965 SCD registers to iwl-prph.h. These registers are assigned from the periphery bus Signed-off-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com> Signed-off-by: Tomas Winkler <tomas.winkler@intel.com> Signed-off-by: Zhu Yi <yi.zhu@intel.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
552 lines
20 KiB
C
552 lines
20 KiB
C
/******************************************************************************
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*
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* This file is provided under a dual BSD/GPLv2 license. When using or
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* redistributing this file, you may do so under either license.
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*
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* GPL LICENSE SUMMARY
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*
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* Copyright(c) 2005 - 2007 Intel Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
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* USA
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*
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* The full GNU General Public License is included in this distribution
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* in the file called LICENSE.GPL.
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*
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* Contact Information:
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* James P. Ketrenos <ipw2100-admin@linux.intel.com>
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* Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
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*
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* BSD LICENSE
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*
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* Copyright(c) 2005 - 2007 Intel Corporation. All rights reserved.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*****************************************************************************/
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#ifndef __iwl_4965_hw_h__
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#define __iwl_4965_hw_h__
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#define IWL_RX_BUF_SIZE (4 * 1024)
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#define IWL_MAX_BSM_SIZE BSM_SRAM_SIZE
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#define KDR_RTC_INST_UPPER_BOUND (0x018000)
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#define KDR_RTC_DATA_UPPER_BOUND (0x80A000)
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#define KDR_RTC_INST_SIZE (KDR_RTC_INST_UPPER_BOUND - RTC_INST_LOWER_BOUND)
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#define KDR_RTC_DATA_SIZE (KDR_RTC_DATA_UPPER_BOUND - RTC_DATA_LOWER_BOUND)
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#define IWL_MAX_INST_SIZE KDR_RTC_INST_SIZE
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#define IWL_MAX_DATA_SIZE KDR_RTC_DATA_SIZE
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static inline int iwl_hw_valid_rtc_data_addr(u32 addr)
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{
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return (addr >= RTC_DATA_LOWER_BOUND) &&
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(addr < KDR_RTC_DATA_UPPER_BOUND);
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}
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/********************* START TXPOWER *****************************************/
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enum {
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HT_IE_EXT_CHANNEL_NONE = 0,
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HT_IE_EXT_CHANNEL_ABOVE,
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HT_IE_EXT_CHANNEL_INVALID,
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HT_IE_EXT_CHANNEL_BELOW,
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HT_IE_EXT_CHANNEL_MAX
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};
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enum {
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CALIB_CH_GROUP_1 = 0,
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CALIB_CH_GROUP_2 = 1,
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CALIB_CH_GROUP_3 = 2,
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CALIB_CH_GROUP_4 = 3,
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CALIB_CH_GROUP_5 = 4,
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CALIB_CH_GROUP_MAX
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};
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/* Temperature calibration offset is 3% 0C in Kelvin */
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#define TEMPERATURE_CALIB_KELVIN_OFFSET 8
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#define TEMPERATURE_CALIB_A_VAL 259
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#define IWL_TX_POWER_TEMPERATURE_MIN (263)
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#define IWL_TX_POWER_TEMPERATURE_MAX (410)
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#define IWL_TX_POWER_TEMPERATURE_OUT_OF_RANGE(t) \
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(((t) < IWL_TX_POWER_TEMPERATURE_MIN) || \
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((t) > IWL_TX_POWER_TEMPERATURE_MAX))
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#define IWL_TX_POWER_ILLEGAL_TEMPERATURE (300)
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#define IWL_TX_POWER_TEMPERATURE_DIFFERENCE (2)
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#define IWL_TX_POWER_MIMO_REGULATORY_COMPENSATION (6)
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#define IWL_TX_POWER_TARGET_POWER_MIN (0) /* 0 dBm = 1 milliwatt */
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#define IWL_TX_POWER_TARGET_POWER_MAX (16) /* 16 dBm */
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/* timeout equivalent to 3 minutes */
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#define IWL_TX_POWER_TIMELIMIT_NOCALIB 1800000000
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#define IWL_TX_POWER_CCK_COMPENSATION (9)
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#define MIN_TX_GAIN_INDEX (0)
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#define MIN_TX_GAIN_INDEX_52GHZ_EXT (-9)
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#define MAX_TX_GAIN_INDEX_52GHZ (98)
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#define MIN_TX_GAIN_52GHZ (98)
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#define MAX_TX_GAIN_INDEX_24GHZ (98)
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#define MIN_TX_GAIN_24GHZ (98)
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#define MAX_TX_GAIN (0)
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#define MAX_TX_GAIN_52GHZ_EXT (-9)
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#define IWL_TX_POWER_DEFAULT_REGULATORY_24 (34)
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#define IWL_TX_POWER_DEFAULT_REGULATORY_52 (34)
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#define IWL_TX_POWER_REGULATORY_MIN (0)
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#define IWL_TX_POWER_REGULATORY_MAX (34)
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#define IWL_TX_POWER_DEFAULT_SATURATION_24 (38)
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#define IWL_TX_POWER_DEFAULT_SATURATION_52 (38)
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#define IWL_TX_POWER_SATURATION_MIN (20)
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#define IWL_TX_POWER_SATURATION_MAX (50)
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/* dv *0.4 = dt; so that 5 degrees temperature diff equals
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* 12.5 in voltage diff */
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#define IWL_TX_TEMPERATURE_UPDATE_LIMIT 9
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#define IWL_INVALID_CHANNEL (0xffffffff)
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#define IWL_TX_POWER_REGITRY_BIT (2)
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#define MIN_IWL_TX_POWER_CALIB_DUR (100)
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#define IWL_CCK_FROM_OFDM_POWER_DIFF (-5)
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#define IWL_CCK_FROM_OFDM_INDEX_DIFF (9)
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/* Number of entries in the gain table */
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#define POWER_GAIN_NUM_ENTRIES 78
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#define TX_POW_MAX_SESSION_NUM 5
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/* timeout equivalent to 3 minutes */
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#define TX_IWL_TIMELIMIT_NOCALIB 1800000000
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/* Kedron TX_CALIB_STATES */
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#define IWL_TX_CALIB_STATE_SEND_TX 0x00000001
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#define IWL_TX_CALIB_WAIT_TX_RESPONSE 0x00000002
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#define IWL_TX_CALIB_ENABLED 0x00000004
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#define IWL_TX_CALIB_XVT_ON 0x00000008
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#define IWL_TX_CALIB_TEMPERATURE_CORRECT 0x00000010
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#define IWL_TX_CALIB_WORKING_WITH_XVT 0x00000020
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#define IWL_TX_CALIB_XVT_PERIODICAL 0x00000040
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#define NUM_IWL_TX_CALIB_SETTINS 5 /* Number of tx correction groups */
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#define IWL_MIN_POWER_IN_VP_TABLE 1 /* 0.5dBm multiplied by 2 */
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#define IWL_MAX_POWER_IN_VP_TABLE 40 /* 20dBm - multiplied by 2 (because
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* entries are for each 0.5dBm) */
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#define IWL_STEP_IN_VP_TABLE 1 /* 0.5dB - multiplied by 2 */
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#define IWL_NUM_POINTS_IN_VPTABLE \
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(1 + IWL_MAX_POWER_IN_VP_TABLE - IWL_MIN_POWER_IN_VP_TABLE)
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#define MIN_TX_GAIN_INDEX (0)
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#define MAX_TX_GAIN_INDEX_52GHZ (98)
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#define MIN_TX_GAIN_52GHZ (98)
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#define MAX_TX_GAIN_INDEX_24GHZ (98)
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#define MIN_TX_GAIN_24GHZ (98)
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#define MAX_TX_GAIN (0)
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/* First and last channels of all groups */
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#define CALIB_IWL_TX_ATTEN_GR1_FCH 34
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#define CALIB_IWL_TX_ATTEN_GR1_LCH 43
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#define CALIB_IWL_TX_ATTEN_GR2_FCH 44
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#define CALIB_IWL_TX_ATTEN_GR2_LCH 70
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#define CALIB_IWL_TX_ATTEN_GR3_FCH 71
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#define CALIB_IWL_TX_ATTEN_GR3_LCH 124
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#define CALIB_IWL_TX_ATTEN_GR4_FCH 125
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#define CALIB_IWL_TX_ATTEN_GR4_LCH 200
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#define CALIB_IWL_TX_ATTEN_GR5_FCH 1
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#define CALIB_IWL_TX_ATTEN_GR5_LCH 20
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union iwl_tx_power_dual_stream {
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struct {
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u8 radio_tx_gain[2];
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u8 dsp_predis_atten[2];
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} s;
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u32 dw;
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};
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/********************* END TXPOWER *****************************************/
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/* HT flags */
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#define RXON_FLG_CTRL_CHANNEL_LOC_POS (22)
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#define RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK __constant_cpu_to_le32(0x1<<22)
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#define RXON_FLG_HT_OPERATING_MODE_POS (23)
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#define RXON_FLG_HT_PROT_MSK __constant_cpu_to_le32(0x1<<23)
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#define RXON_FLG_FAT_PROT_MSK __constant_cpu_to_le32(0x2<<23)
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#define RXON_FLG_CHANNEL_MODE_POS (25)
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#define RXON_FLG_CHANNEL_MODE_MSK __constant_cpu_to_le32(0x3<<25)
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#define RXON_FLG_CHANNEL_MODE_PURE_40_MSK __constant_cpu_to_le32(0x1<<25)
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#define RXON_FLG_CHANNEL_MODE_MIXED_MSK __constant_cpu_to_le32(0x2<<25)
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#define RXON_RX_CHAIN_DRIVER_FORCE_MSK __constant_cpu_to_le16(0x1<<0)
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#define RXON_RX_CHAIN_VALID_MSK __constant_cpu_to_le16(0x7<<1)
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#define RXON_RX_CHAIN_VALID_POS (1)
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#define RXON_RX_CHAIN_FORCE_SEL_MSK __constant_cpu_to_le16(0x7<<4)
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#define RXON_RX_CHAIN_FORCE_SEL_POS (4)
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#define RXON_RX_CHAIN_FORCE_MIMO_SEL_MSK __constant_cpu_to_le16(0x7<<7)
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#define RXON_RX_CHAIN_FORCE_MIMO_SEL_POS (7)
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#define RXON_RX_CHAIN_CNT_MSK __constant_cpu_to_le16(0x3<<10)
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#define RXON_RX_CHAIN_CNT_POS (10)
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#define RXON_RX_CHAIN_MIMO_CNT_MSK __constant_cpu_to_le16(0x3<<12)
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#define RXON_RX_CHAIN_MIMO_CNT_POS (12)
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#define RXON_RX_CHAIN_MIMO_FORCE_MSK __constant_cpu_to_le16(0x1<<14)
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#define RXON_RX_CHAIN_MIMO_FORCE_POS (14)
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#define MCS_DUP_6M_PLCP 0x20
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/* OFDM HT rate masks */
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/* ***************************************** */
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#define R_MCS_6M_MSK 0x1
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#define R_MCS_12M_MSK 0x2
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#define R_MCS_18M_MSK 0x4
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#define R_MCS_24M_MSK 0x8
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#define R_MCS_36M_MSK 0x10
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#define R_MCS_48M_MSK 0x20
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#define R_MCS_54M_MSK 0x40
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#define R_MCS_60M_MSK 0x80
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#define R_MCS_12M_DUAL_MSK 0x100
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#define R_MCS_24M_DUAL_MSK 0x200
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#define R_MCS_36M_DUAL_MSK 0x400
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#define R_MCS_48M_DUAL_MSK 0x800
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#define is_legacy(tbl) (((tbl) == LQ_G) || ((tbl) == LQ_A))
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#define is_siso(tbl) (((tbl) == LQ_SISO))
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#define is_mimo(tbl) (((tbl) == LQ_MIMO))
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#define is_Ht(tbl) (is_siso(tbl) || is_mimo(tbl))
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#define is_a_band(tbl) (((tbl) == LQ_A))
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#define is_g_and(tbl) (((tbl) == LQ_G))
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/* Flow Handler Definitions */
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/**********************/
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/* Addresses */
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/**********************/
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#define FH_MEM_LOWER_BOUND (0x1000)
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#define FH_MEM_UPPER_BOUND (0x1EF0)
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#define IWL_FH_REGS_LOWER_BOUND (0x1000)
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#define IWL_FH_REGS_UPPER_BOUND (0x2000)
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#define IWL_FH_KW_MEM_ADDR_REG (FH_MEM_LOWER_BOUND + 0x97C)
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/* CBBC Area - Circular buffers base address cache pointers table */
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#define FH_MEM_CBBC_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0x9D0)
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#define FH_MEM_CBBC_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xA10)
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/* queues 0 - 15 */
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#define FH_MEM_CBBC_QUEUE(x) (FH_MEM_CBBC_LOWER_BOUND + (x) * 0x4)
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/* RSCSR Area */
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#define FH_MEM_RSCSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xBC0)
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#define FH_MEM_RSCSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xC00)
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#define FH_MEM_RSCSR_CHNL0 (FH_MEM_RSCSR_LOWER_BOUND)
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#define FH_RSCSR_CHNL0_STTS_WPTR_REG (FH_MEM_RSCSR_CHNL0)
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#define FH_RSCSR_CHNL0_RBDCB_BASE_REG (FH_MEM_RSCSR_CHNL0 + 0x004)
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#define FH_RSCSR_CHNL0_RBDCB_WPTR_REG (FH_MEM_RSCSR_CHNL0 + 0x008)
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/* RCSR Area - Registers address map */
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#define FH_MEM_RCSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xC00)
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#define FH_MEM_RCSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xCC0)
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#define FH_MEM_RCSR_CHNL0 (FH_MEM_RCSR_LOWER_BOUND)
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#define FH_MEM_RCSR_CHNL0_CONFIG_REG (FH_MEM_RCSR_CHNL0)
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/* RSSR Area - Rx shared ctrl & status registers */
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#define FH_MEM_RSSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xC40)
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#define FH_MEM_RSSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xD00)
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#define FH_MEM_RSSR_SHARED_CTRL_REG (FH_MEM_RSSR_LOWER_BOUND)
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#define FH_MEM_RSSR_RX_STATUS_REG (FH_MEM_RSSR_LOWER_BOUND + 0x004)
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#define FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV (FH_MEM_RSSR_LOWER_BOUND + 0x008)
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/* TCSR */
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#define IWL_FH_TCSR_LOWER_BOUND (IWL_FH_REGS_LOWER_BOUND + 0xD00)
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#define IWL_FH_TCSR_UPPER_BOUND (IWL_FH_REGS_LOWER_BOUND + 0xE60)
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#define IWL_FH_TCSR_CHNL_NUM (7)
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#define IWL_FH_TCSR_CHNL_TX_CONFIG_REG(_chnl) \
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(IWL_FH_TCSR_LOWER_BOUND + 0x20 * _chnl)
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/* TSSR Area - Tx shared status registers */
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/* TSSR */
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#define IWL_FH_TSSR_LOWER_BOUND (IWL_FH_REGS_LOWER_BOUND + 0xEA0)
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#define IWL_FH_TSSR_UPPER_BOUND (IWL_FH_REGS_LOWER_BOUND + 0xEC0)
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#define IWL_FH_TSSR_TX_MSG_CONFIG_REG (IWL_FH_TSSR_LOWER_BOUND + 0x008)
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#define IWL_FH_TSSR_TX_STATUS_REG (IWL_FH_TSSR_LOWER_BOUND + 0x010)
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#define IWL_FH_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON (0xFF000000)
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#define IWL_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON (0x00FF0000)
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#define IWL_FH_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_64B (0x00000000)
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#define IWL_FH_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B (0x00000400)
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#define IWL_FH_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_256B (0x00000800)
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#define IWL_FH_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_512B (0x00000C00)
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#define IWL_FH_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON (0x00000100)
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#define IWL_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON (0x00000080)
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#define IWL_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH (0x00000020)
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#define IWL_FH_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH (0x00000005)
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#define IWL_FH_TSSR_TX_STATUS_REG_BIT_BUFS_EMPTY(_chnl) \
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((1 << (_chnl)) << 24)
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#define IWL_FH_TSSR_TX_STATUS_REG_BIT_NO_PEND_REQ(_chnl) \
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((1 << (_chnl)) << 16)
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#define IWL_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_chnl) \
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(IWL_FH_TSSR_TX_STATUS_REG_BIT_BUFS_EMPTY(_chnl) | \
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IWL_FH_TSSR_TX_STATUS_REG_BIT_NO_PEND_REQ(_chnl))
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/* TCSR: tx_config register values */
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#define IWL_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF (0x00000000)
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#define IWL_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_DRIVER (0x00000001)
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#define IWL_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_ARC (0x00000002)
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#define IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE_VAL (0x00000000)
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#define IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL (0x00000008)
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#define IWL_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_NOINT (0x00000000)
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#define IWL_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD (0x00100000)
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#define IWL_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD (0x00200000)
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#define IWL_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT (0x00000000)
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#define IWL_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_ENDTFD (0x00400000)
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#define IWL_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_IFTFD (0x00800000)
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#define IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE (0x00000000)
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#define IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE_EOF (0x40000000)
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#define IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE (0x80000000)
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#define IWL_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_EMPTY (0x00000000)
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#define IWL_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_WAIT (0x00002000)
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#define IWL_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID (0x00000003)
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#define IWL_FH_TCSR_CHNL_TX_BUF_STS_REG_BIT_TFDB_WPTR (0x00000001)
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#define IWL_FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM (20)
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#define IWL_FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX (12)
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/* RCSR: channel 0 rx_config register defines */
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#define FH_RCSR_CHNL0_RX_CONFIG_DMA_CHNL_EN_MASK (0xC0000000) /* bits 30-31 */
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#define FH_RCSR_CHNL0_RX_CONFIG_RBDBC_SIZE_MASK (0x00F00000) /* bits 20-23 */
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#define FH_RCSR_CHNL0_RX_CONFIG_RB_SIZE_MASK (0x00030000) /* bits 16-17 */
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#define FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MASK (0x00008000) /* bit 15 */
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#define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_MASK (0x00001000) /* bit 12 */
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#define FH_RCSR_CHNL0_RX_CONFIG_RB_TIMEOUT_MASK (0x00000FF0) /* bit 4-11 */
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#define FH_RCSR_RX_CONFIG_RBDCB_SIZE_BITSHIFT (20)
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#define FH_RCSR_RX_CONFIG_RB_SIZE_BITSHIFT (16)
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/* RCSR: rx_config register values */
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#define FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_VAL (0x00000000)
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#define FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_EOF_VAL (0x40000000)
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#define FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL (0x80000000)
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#define IWL_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K (0x00000000)
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/* RCSR channel 0 config register values */
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#define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_NO_INT_VAL (0x00000000)
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#define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL (0x00001000)
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/* RSCSR: defs used in normal mode */
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#define FH_RSCSR_CHNL0_RBDCB_WPTR_MASK (0x00000FFF) /* bits 0-11 */
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#define SCD_WIN_SIZE 64
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#define SCD_FRAME_LIMIT 64
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/* SRAM structures */
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#define SCD_CONTEXT_DATA_OFFSET 0x380
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#define SCD_TX_STTS_BITMAP_OFFSET 0x400
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#define SCD_TRANSLATE_TBL_OFFSET 0x500
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#define SCD_CONTEXT_QUEUE_OFFSET(x) (SCD_CONTEXT_DATA_OFFSET + ((x) * 8))
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#define SCD_TRANSLATE_TBL_OFFSET_QUEUE(x) \
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((SCD_TRANSLATE_TBL_OFFSET + ((x) * 2)) & 0xfffffffc)
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#define SCD_TXFACT_REG_TXFIFO_MASK(lo, hi) \
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((1<<(hi))|((1<<(hi))-(1<<(lo))))
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#define SCD_MODE_REG_BIT_SEARCH_MODE (1<<0)
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#define SCD_MODE_REG_BIT_SBYP_MODE (1<<1)
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#define SCD_TXFIFO_POS_TID (0)
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#define SCD_TXFIFO_POS_RA (4)
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#define SCD_QUEUE_STTS_REG_POS_ACTIVE (0)
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#define SCD_QUEUE_STTS_REG_POS_TXF (1)
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#define SCD_QUEUE_STTS_REG_POS_WSL (5)
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#define SCD_QUEUE_STTS_REG_POS_SCD_ACK (8)
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#define SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN (10)
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#define SCD_QUEUE_STTS_REG_MSK (0x0007FC00)
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#define SCD_QUEUE_RA_TID_MAP_RATID_MSK (0x01FF)
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#define SCD_QUEUE_CTX_REG1_WIN_SIZE_POS (0)
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#define SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK (0x0000007F)
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#define SCD_QUEUE_CTX_REG1_CREDIT_POS (8)
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#define SCD_QUEUE_CTX_REG1_CREDIT_MSK (0x00FFFF00)
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#define SCD_QUEUE_CTX_REG1_SUPER_CREDIT_POS (24)
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#define SCD_QUEUE_CTX_REG1_SUPER_CREDIT_MSK (0xFF000000)
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#define SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS (16)
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#define SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK (0x007F0000)
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#define CSR_HW_IF_CONFIG_REG_BIT_KEDRON_R (0x00000010)
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#define CSR_HW_IF_CONFIG_REG_MSK_BOARD_VER (0x00000C00)
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#define CSR_HW_IF_CONFIG_REG_BIT_MAC_SI (0x00000100)
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#define CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI (0x00000200)
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static inline u8 iwl_hw_get_rate(__le32 rate_n_flags)
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{
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return le32_to_cpu(rate_n_flags) & 0xFF;
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}
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static inline u16 iwl_hw_get_rate_n_flags(__le32 rate_n_flags)
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{
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return le32_to_cpu(rate_n_flags) & 0xFFFF;
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}
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static inline __le32 iwl_hw_set_rate_n_flags(u8 rate, u16 flags)
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{
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return cpu_to_le32(flags|(u16)rate);
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}
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struct iwl_tfd_frame_data {
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__le32 tb1_addr;
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__le32 val1;
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/* __le32 ptb1_32_35:4; */
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#define IWL_tb1_addr_hi_POS 0
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#define IWL_tb1_addr_hi_LEN 4
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#define IWL_tb1_addr_hi_SYM val1
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/* __le32 tb_len1:12; */
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#define IWL_tb1_len_POS 4
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#define IWL_tb1_len_LEN 12
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#define IWL_tb1_len_SYM val1
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/* __le32 ptb2_0_15:16; */
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#define IWL_tb2_addr_lo16_POS 16
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#define IWL_tb2_addr_lo16_LEN 16
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#define IWL_tb2_addr_lo16_SYM val1
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__le32 val2;
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/* __le32 ptb2_16_35:20; */
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#define IWL_tb2_addr_hi20_POS 0
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#define IWL_tb2_addr_hi20_LEN 20
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#define IWL_tb2_addr_hi20_SYM val2
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/* __le32 tb_len2:12; */
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#define IWL_tb2_len_POS 20
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#define IWL_tb2_len_LEN 12
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#define IWL_tb2_len_SYM val2
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} __attribute__ ((packed));
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struct iwl_tfd_frame {
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__le32 val0;
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/* __le32 rsvd1:24; */
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/* __le32 num_tbs:5; */
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#define IWL_num_tbs_POS 24
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#define IWL_num_tbs_LEN 5
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#define IWL_num_tbs_SYM val0
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/* __le32 rsvd2:1; */
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/* __le32 padding:2; */
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struct iwl_tfd_frame_data pa[10];
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__le32 reserved;
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} __attribute__ ((packed));
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#define IWL4965_MAX_WIN_SIZE 64
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#define IWL4965_QUEUE_SIZE 256
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#define IWL4965_NUM_FIFOS 7
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#define IWL_MAX_NUM_QUEUES 16
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struct iwl4965_queue_byte_cnt_entry {
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__le16 val;
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/* __le16 byte_cnt:12; */
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#define IWL_byte_cnt_POS 0
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#define IWL_byte_cnt_LEN 12
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#define IWL_byte_cnt_SYM val
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/* __le16 rsvd:4; */
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} __attribute__ ((packed));
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struct iwl4965_sched_queue_byte_cnt_tbl {
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struct iwl4965_queue_byte_cnt_entry tfd_offset[IWL4965_QUEUE_SIZE +
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IWL4965_MAX_WIN_SIZE];
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u8 dont_care[1024 -
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(IWL4965_QUEUE_SIZE + IWL4965_MAX_WIN_SIZE) *
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sizeof(__le16)];
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} __attribute__ ((packed));
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/* Base physical address of iwl_shared is provided to KDR_SCD_DRAM_BASE_ADDR
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* and &iwl_shared.val0 is provided to FH_RSCSR_CHNL0_STTS_WPTR_REG */
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struct iwl_shared {
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struct iwl4965_sched_queue_byte_cnt_tbl
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queues_byte_cnt_tbls[IWL_MAX_NUM_QUEUES];
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__le32 val0;
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/* __le32 rb_closed_stts_rb_num:12; */
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#define IWL_rb_closed_stts_rb_num_POS 0
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#define IWL_rb_closed_stts_rb_num_LEN 12
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#define IWL_rb_closed_stts_rb_num_SYM val0
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/* __le32 rsrv1:4; */
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/* __le32 rb_closed_stts_rx_frame_num:12; */
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#define IWL_rb_closed_stts_rx_frame_num_POS 16
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#define IWL_rb_closed_stts_rx_frame_num_LEN 12
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#define IWL_rb_closed_stts_rx_frame_num_SYM val0
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/* __le32 rsrv2:4; */
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__le32 val1;
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/* __le32 frame_finished_stts_rb_num:12; */
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#define IWL_frame_finished_stts_rb_num_POS 0
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#define IWL_frame_finished_stts_rb_num_LEN 12
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#define IWL_frame_finished_stts_rb_num_SYM val1
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/* __le32 rsrv3:4; */
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/* __le32 frame_finished_stts_rx_frame_num:12; */
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#define IWL_frame_finished_stts_rx_frame_num_POS 16
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#define IWL_frame_finished_stts_rx_frame_num_LEN 12
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#define IWL_frame_finished_stts_rx_frame_num_SYM val1
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/* __le32 rsrv4:4; */
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|
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__le32 padding1; /* so that allocation will be aligned to 16B */
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__le32 padding2;
|
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} __attribute__ ((packed));
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#endif /* __iwl_4965_hw_h__ */
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