forked from Minki/linux
e9eef1e596
Qualcomm chipsets have QUSB2 phy controller that provides HighSpeed functionality for DWC3 controller. Adding dt binding information for the same. Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
44 lines
1.3 KiB
Plaintext
44 lines
1.3 KiB
Plaintext
Qualcomm QUSB2 phy controller
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QUSB2 controller supports LS/FS/HS usb connectivity on Qualcomm chipsets.
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Required properties:
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- compatible: compatible list, contains "qcom,msm8996-qusb2-phy".
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- reg: offset and length of the PHY register set.
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- #phy-cells: must be 0.
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- clocks: a list of phandles and clock-specifier pairs,
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one for each entry in clock-names.
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- clock-names: must be "cfg_ahb" for phy config clock,
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"ref" for 19.2 MHz ref clk,
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"iface" for phy interface clock (Optional).
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- vdda-pll-supply: Phandle to 1.8V regulator supply to PHY refclk pll block.
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- vdda-phy-dpdm-supply: Phandle to 3.1V regulator supply to Dp/Dm port signals.
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- resets: Phandle to reset to phy block.
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Optional properties:
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- nvmem-cells: Phandle to nvmem cell that contains 'HS Tx trim'
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tuning parameter value for qusb2 phy.
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- qcom,tcsr-syscon: Phandle to TCSR syscon register region.
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Example:
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hsusb_phy: phy@7411000 {
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compatible = "qcom,msm8996-qusb2-phy";
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reg = <0x7411000 0x180>;
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#phy-cells = <0>;
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clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
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<&gcc GCC_RX1_USB2_CLKREF_CLK>,
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clock-names = "cfg_ahb", "ref";
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vdda-pll-supply = <&pm8994_l12>;
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vdda-phy-dpdm-supply = <&pm8994_l24>;
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resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
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nvmem-cells = <&qusb2p_hstx_trim>;
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};
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