forked from Minki/linux
edadced2bc
dwapb_irq_set_type overwrites polarity register value for IRQ_TYPE_EDGE_BOTH case. If the polarity of one gpio is 0 by default, then it will set falling edge irq trigger. and the gpio may requires rising edge irq for the first time, and it will be missed. Do not overwrite polarity register for IRQ_TYPE_EDGE_BOTH case can solve this issue. Signed-off-by: Xiaoguang Chen <xgchenshy@gmail.com> Tested-by: Jisheng Zhang <jszhang@marvell.com> [Fix some really weird text encoding problem] Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
772 lines
19 KiB
C
772 lines
19 KiB
C
/*
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* Copyright (c) 2011 Jamie Iles
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* All enquiries to support@picochip.com
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*/
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#include <linux/acpi.h>
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#include <linux/gpio/driver.h>
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/* FIXME: for gpio_get_value(), replace this with direct register read */
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#include <linux/gpio.h>
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/ioport.h>
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#include <linux/irq.h>
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#include <linux/irqdomain.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/of_irq.h>
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#include <linux/platform_device.h>
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#include <linux/property.h>
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#include <linux/spinlock.h>
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#include <linux/platform_data/gpio-dwapb.h>
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#include <linux/slab.h>
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#include "gpiolib.h"
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#define GPIO_SWPORTA_DR 0x00
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#define GPIO_SWPORTA_DDR 0x04
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#define GPIO_SWPORTB_DR 0x0c
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#define GPIO_SWPORTB_DDR 0x10
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#define GPIO_SWPORTC_DR 0x18
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#define GPIO_SWPORTC_DDR 0x1c
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#define GPIO_SWPORTD_DR 0x24
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#define GPIO_SWPORTD_DDR 0x28
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#define GPIO_INTEN 0x30
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#define GPIO_INTMASK 0x34
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#define GPIO_INTTYPE_LEVEL 0x38
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#define GPIO_INT_POLARITY 0x3c
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#define GPIO_INTSTATUS 0x40
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#define GPIO_PORTA_DEBOUNCE 0x48
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#define GPIO_PORTA_EOI 0x4c
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#define GPIO_EXT_PORTA 0x50
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#define GPIO_EXT_PORTB 0x54
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#define GPIO_EXT_PORTC 0x58
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#define GPIO_EXT_PORTD 0x5c
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#define DWAPB_MAX_PORTS 4
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#define GPIO_EXT_PORT_SIZE (GPIO_EXT_PORTB - GPIO_EXT_PORTA)
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#define GPIO_SWPORT_DR_SIZE (GPIO_SWPORTB_DR - GPIO_SWPORTA_DR)
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#define GPIO_SWPORT_DDR_SIZE (GPIO_SWPORTB_DDR - GPIO_SWPORTA_DDR)
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#define GPIO_REG_OFFSET_V2 1
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#define GPIO_INTMASK_V2 0x44
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#define GPIO_INTTYPE_LEVEL_V2 0x34
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#define GPIO_INT_POLARITY_V2 0x38
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#define GPIO_INTSTATUS_V2 0x3c
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#define GPIO_PORTA_EOI_V2 0x40
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struct dwapb_gpio;
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#ifdef CONFIG_PM_SLEEP
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/* Store GPIO context across system-wide suspend/resume transitions */
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struct dwapb_context {
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u32 data;
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u32 dir;
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u32 ext;
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u32 int_en;
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u32 int_mask;
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u32 int_type;
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u32 int_pol;
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u32 int_deb;
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};
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#endif
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struct dwapb_gpio_port {
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struct gpio_chip gc;
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bool is_registered;
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struct dwapb_gpio *gpio;
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#ifdef CONFIG_PM_SLEEP
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struct dwapb_context *ctx;
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#endif
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unsigned int idx;
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};
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struct dwapb_gpio {
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struct device *dev;
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void __iomem *regs;
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struct dwapb_gpio_port *ports;
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unsigned int nr_ports;
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struct irq_domain *domain;
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unsigned int flags;
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};
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static inline u32 gpio_reg_v2_convert(unsigned int offset)
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{
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switch (offset) {
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case GPIO_INTMASK:
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return GPIO_INTMASK_V2;
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case GPIO_INTTYPE_LEVEL:
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return GPIO_INTTYPE_LEVEL_V2;
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case GPIO_INT_POLARITY:
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return GPIO_INT_POLARITY_V2;
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case GPIO_INTSTATUS:
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return GPIO_INTSTATUS_V2;
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case GPIO_PORTA_EOI:
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return GPIO_PORTA_EOI_V2;
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}
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return offset;
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}
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static inline u32 gpio_reg_convert(struct dwapb_gpio *gpio, unsigned int offset)
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{
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if (gpio->flags & GPIO_REG_OFFSET_V2)
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return gpio_reg_v2_convert(offset);
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return offset;
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}
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static inline u32 dwapb_read(struct dwapb_gpio *gpio, unsigned int offset)
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{
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struct gpio_chip *gc = &gpio->ports[0].gc;
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void __iomem *reg_base = gpio->regs;
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return gc->read_reg(reg_base + gpio_reg_convert(gpio, offset));
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}
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static inline void dwapb_write(struct dwapb_gpio *gpio, unsigned int offset,
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u32 val)
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{
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struct gpio_chip *gc = &gpio->ports[0].gc;
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void __iomem *reg_base = gpio->regs;
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gc->write_reg(reg_base + gpio_reg_convert(gpio, offset), val);
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}
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static int dwapb_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
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{
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struct dwapb_gpio_port *port = gpiochip_get_data(gc);
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struct dwapb_gpio *gpio = port->gpio;
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return irq_find_mapping(gpio->domain, offset);
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}
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static void dwapb_toggle_trigger(struct dwapb_gpio *gpio, unsigned int offs)
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{
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u32 v = dwapb_read(gpio, GPIO_INT_POLARITY);
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if (gpio_get_value(gpio->ports[0].gc.base + offs))
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v &= ~BIT(offs);
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else
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v |= BIT(offs);
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dwapb_write(gpio, GPIO_INT_POLARITY, v);
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}
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static u32 dwapb_do_irq(struct dwapb_gpio *gpio)
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{
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u32 irq_status = dwapb_read(gpio, GPIO_INTSTATUS);
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u32 ret = irq_status;
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while (irq_status) {
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int hwirq = fls(irq_status) - 1;
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int gpio_irq = irq_find_mapping(gpio->domain, hwirq);
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generic_handle_irq(gpio_irq);
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irq_status &= ~BIT(hwirq);
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if ((irq_get_trigger_type(gpio_irq) & IRQ_TYPE_SENSE_MASK)
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== IRQ_TYPE_EDGE_BOTH)
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dwapb_toggle_trigger(gpio, hwirq);
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}
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return ret;
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}
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static void dwapb_irq_handler(struct irq_desc *desc)
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{
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struct dwapb_gpio *gpio = irq_desc_get_handler_data(desc);
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struct irq_chip *chip = irq_desc_get_chip(desc);
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dwapb_do_irq(gpio);
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if (chip->irq_eoi)
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chip->irq_eoi(irq_desc_get_irq_data(desc));
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}
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static void dwapb_irq_enable(struct irq_data *d)
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{
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struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
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struct dwapb_gpio *gpio = igc->private;
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struct gpio_chip *gc = &gpio->ports[0].gc;
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unsigned long flags;
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u32 val;
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spin_lock_irqsave(&gc->bgpio_lock, flags);
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val = dwapb_read(gpio, GPIO_INTEN);
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val |= BIT(d->hwirq);
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dwapb_write(gpio, GPIO_INTEN, val);
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spin_unlock_irqrestore(&gc->bgpio_lock, flags);
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}
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static void dwapb_irq_disable(struct irq_data *d)
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{
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struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
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struct dwapb_gpio *gpio = igc->private;
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struct gpio_chip *gc = &gpio->ports[0].gc;
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unsigned long flags;
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u32 val;
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spin_lock_irqsave(&gc->bgpio_lock, flags);
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val = dwapb_read(gpio, GPIO_INTEN);
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val &= ~BIT(d->hwirq);
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dwapb_write(gpio, GPIO_INTEN, val);
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spin_unlock_irqrestore(&gc->bgpio_lock, flags);
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}
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static int dwapb_irq_reqres(struct irq_data *d)
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{
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struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
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struct dwapb_gpio *gpio = igc->private;
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struct gpio_chip *gc = &gpio->ports[0].gc;
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if (gpiochip_lock_as_irq(gc, irqd_to_hwirq(d))) {
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dev_err(gpio->dev, "unable to lock HW IRQ %lu for IRQ\n",
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irqd_to_hwirq(d));
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return -EINVAL;
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}
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return 0;
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}
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static void dwapb_irq_relres(struct irq_data *d)
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{
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struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
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struct dwapb_gpio *gpio = igc->private;
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struct gpio_chip *gc = &gpio->ports[0].gc;
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gpiochip_unlock_as_irq(gc, irqd_to_hwirq(d));
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}
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static int dwapb_irq_set_type(struct irq_data *d, u32 type)
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{
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struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
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struct dwapb_gpio *gpio = igc->private;
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struct gpio_chip *gc = &gpio->ports[0].gc;
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int bit = d->hwirq;
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unsigned long level, polarity, flags;
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if (type & ~(IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
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IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
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return -EINVAL;
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spin_lock_irqsave(&gc->bgpio_lock, flags);
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level = dwapb_read(gpio, GPIO_INTTYPE_LEVEL);
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polarity = dwapb_read(gpio, GPIO_INT_POLARITY);
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switch (type) {
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case IRQ_TYPE_EDGE_BOTH:
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level |= BIT(bit);
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dwapb_toggle_trigger(gpio, bit);
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break;
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case IRQ_TYPE_EDGE_RISING:
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level |= BIT(bit);
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polarity |= BIT(bit);
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break;
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case IRQ_TYPE_EDGE_FALLING:
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level |= BIT(bit);
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polarity &= ~BIT(bit);
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break;
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case IRQ_TYPE_LEVEL_HIGH:
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level &= ~BIT(bit);
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polarity |= BIT(bit);
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break;
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case IRQ_TYPE_LEVEL_LOW:
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level &= ~BIT(bit);
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polarity &= ~BIT(bit);
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break;
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}
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irq_setup_alt_chip(d, type);
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dwapb_write(gpio, GPIO_INTTYPE_LEVEL, level);
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if (type != IRQ_TYPE_EDGE_BOTH)
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dwapb_write(gpio, GPIO_INT_POLARITY, polarity);
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spin_unlock_irqrestore(&gc->bgpio_lock, flags);
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return 0;
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}
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static int dwapb_gpio_set_debounce(struct gpio_chip *gc,
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unsigned offset, unsigned debounce)
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{
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struct dwapb_gpio_port *port = gpiochip_get_data(gc);
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struct dwapb_gpio *gpio = port->gpio;
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unsigned long flags, val_deb;
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unsigned long mask = gc->pin2mask(gc, offset);
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spin_lock_irqsave(&gc->bgpio_lock, flags);
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val_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE);
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if (debounce)
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dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, val_deb | mask);
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else
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dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, val_deb & ~mask);
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spin_unlock_irqrestore(&gc->bgpio_lock, flags);
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return 0;
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}
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static int dwapb_gpio_set_config(struct gpio_chip *gc, unsigned offset,
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unsigned long config)
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{
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u32 debounce;
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if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
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return -ENOTSUPP;
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debounce = pinconf_to_config_argument(config);
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return dwapb_gpio_set_debounce(gc, offset, debounce);
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}
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static irqreturn_t dwapb_irq_handler_mfd(int irq, void *dev_id)
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{
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u32 worked;
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struct dwapb_gpio *gpio = dev_id;
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worked = dwapb_do_irq(gpio);
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return worked ? IRQ_HANDLED : IRQ_NONE;
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}
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static void dwapb_configure_irqs(struct dwapb_gpio *gpio,
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struct dwapb_gpio_port *port,
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struct dwapb_port_property *pp)
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{
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struct gpio_chip *gc = &port->gc;
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struct fwnode_handle *fwnode = pp->fwnode;
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struct irq_chip_generic *irq_gc = NULL;
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unsigned int hwirq, ngpio = gc->ngpio;
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struct irq_chip_type *ct;
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int err, i;
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gpio->domain = irq_domain_create_linear(fwnode, ngpio,
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&irq_generic_chip_ops, gpio);
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if (!gpio->domain)
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return;
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err = irq_alloc_domain_generic_chips(gpio->domain, ngpio, 2,
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"gpio-dwapb", handle_level_irq,
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IRQ_NOREQUEST, 0,
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IRQ_GC_INIT_NESTED_LOCK);
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if (err) {
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dev_info(gpio->dev, "irq_alloc_domain_generic_chips failed\n");
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irq_domain_remove(gpio->domain);
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gpio->domain = NULL;
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return;
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}
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irq_gc = irq_get_domain_generic_chip(gpio->domain, 0);
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if (!irq_gc) {
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irq_domain_remove(gpio->domain);
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gpio->domain = NULL;
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return;
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}
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irq_gc->reg_base = gpio->regs;
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irq_gc->private = gpio;
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for (i = 0; i < 2; i++) {
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ct = &irq_gc->chip_types[i];
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ct->chip.irq_ack = irq_gc_ack_set_bit;
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ct->chip.irq_mask = irq_gc_mask_set_bit;
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ct->chip.irq_unmask = irq_gc_mask_clr_bit;
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ct->chip.irq_set_type = dwapb_irq_set_type;
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ct->chip.irq_enable = dwapb_irq_enable;
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ct->chip.irq_disable = dwapb_irq_disable;
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ct->chip.irq_request_resources = dwapb_irq_reqres;
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ct->chip.irq_release_resources = dwapb_irq_relres;
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ct->regs.ack = gpio_reg_convert(gpio, GPIO_PORTA_EOI);
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ct->regs.mask = gpio_reg_convert(gpio, GPIO_INTMASK);
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ct->type = IRQ_TYPE_LEVEL_MASK;
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}
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irq_gc->chip_types[0].type = IRQ_TYPE_LEVEL_MASK;
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irq_gc->chip_types[1].type = IRQ_TYPE_EDGE_BOTH;
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irq_gc->chip_types[1].handler = handle_edge_irq;
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if (!pp->irq_shared) {
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irq_set_chained_handler_and_data(pp->irq, dwapb_irq_handler,
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gpio);
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} else {
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/*
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* Request a shared IRQ since where MFD would have devices
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* using the same irq pin
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*/
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err = devm_request_irq(gpio->dev, pp->irq,
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dwapb_irq_handler_mfd,
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IRQF_SHARED, "gpio-dwapb-mfd", gpio);
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if (err) {
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dev_err(gpio->dev, "error requesting IRQ\n");
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irq_domain_remove(gpio->domain);
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gpio->domain = NULL;
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return;
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}
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}
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for (hwirq = 0 ; hwirq < ngpio ; hwirq++)
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irq_create_mapping(gpio->domain, hwirq);
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port->gc.to_irq = dwapb_gpio_to_irq;
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}
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static void dwapb_irq_teardown(struct dwapb_gpio *gpio)
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{
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struct dwapb_gpio_port *port = &gpio->ports[0];
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struct gpio_chip *gc = &port->gc;
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unsigned int ngpio = gc->ngpio;
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irq_hw_number_t hwirq;
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if (!gpio->domain)
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return;
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for (hwirq = 0 ; hwirq < ngpio ; hwirq++)
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irq_dispose_mapping(irq_find_mapping(gpio->domain, hwirq));
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irq_domain_remove(gpio->domain);
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gpio->domain = NULL;
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}
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static int dwapb_gpio_add_port(struct dwapb_gpio *gpio,
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struct dwapb_port_property *pp,
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unsigned int offs)
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{
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struct dwapb_gpio_port *port;
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void __iomem *dat, *set, *dirout;
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int err;
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port = &gpio->ports[offs];
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port->gpio = gpio;
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port->idx = pp->idx;
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#ifdef CONFIG_PM_SLEEP
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port->ctx = devm_kzalloc(gpio->dev, sizeof(*port->ctx), GFP_KERNEL);
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if (!port->ctx)
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return -ENOMEM;
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#endif
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dat = gpio->regs + GPIO_EXT_PORTA + (pp->idx * GPIO_EXT_PORT_SIZE);
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set = gpio->regs + GPIO_SWPORTA_DR + (pp->idx * GPIO_SWPORT_DR_SIZE);
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dirout = gpio->regs + GPIO_SWPORTA_DDR +
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(pp->idx * GPIO_SWPORT_DDR_SIZE);
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err = bgpio_init(&port->gc, gpio->dev, 4, dat, set, NULL, dirout,
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NULL, false);
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if (err) {
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dev_err(gpio->dev, "failed to init gpio chip for port%d\n",
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port->idx);
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return err;
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}
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#ifdef CONFIG_OF_GPIO
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port->gc.of_node = to_of_node(pp->fwnode);
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#endif
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port->gc.ngpio = pp->ngpio;
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port->gc.base = pp->gpio_base;
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|
|
|
/* Only port A support debounce */
|
|
if (pp->idx == 0)
|
|
port->gc.set_config = dwapb_gpio_set_config;
|
|
|
|
if (pp->irq)
|
|
dwapb_configure_irqs(gpio, port, pp);
|
|
|
|
err = gpiochip_add_data(&port->gc, port);
|
|
if (err)
|
|
dev_err(gpio->dev, "failed to register gpiochip for port%d\n",
|
|
port->idx);
|
|
else
|
|
port->is_registered = true;
|
|
|
|
/* Add GPIO-signaled ACPI event support */
|
|
if (pp->irq)
|
|
acpi_gpiochip_request_interrupts(&port->gc);
|
|
|
|
return err;
|
|
}
|
|
|
|
static void dwapb_gpio_unregister(struct dwapb_gpio *gpio)
|
|
{
|
|
unsigned int m;
|
|
|
|
for (m = 0; m < gpio->nr_ports; ++m)
|
|
if (gpio->ports[m].is_registered)
|
|
gpiochip_remove(&gpio->ports[m].gc);
|
|
}
|
|
|
|
static struct dwapb_platform_data *
|
|
dwapb_gpio_get_pdata(struct device *dev)
|
|
{
|
|
struct fwnode_handle *fwnode;
|
|
struct dwapb_platform_data *pdata;
|
|
struct dwapb_port_property *pp;
|
|
int nports;
|
|
int i;
|
|
|
|
nports = device_get_child_node_count(dev);
|
|
if (nports == 0)
|
|
return ERR_PTR(-ENODEV);
|
|
|
|
pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
|
|
if (!pdata)
|
|
return ERR_PTR(-ENOMEM);
|
|
|
|
pdata->properties = devm_kcalloc(dev, nports, sizeof(*pp), GFP_KERNEL);
|
|
if (!pdata->properties)
|
|
return ERR_PTR(-ENOMEM);
|
|
|
|
pdata->nports = nports;
|
|
|
|
i = 0;
|
|
device_for_each_child_node(dev, fwnode) {
|
|
pp = &pdata->properties[i++];
|
|
pp->fwnode = fwnode;
|
|
|
|
if (fwnode_property_read_u32(fwnode, "reg", &pp->idx) ||
|
|
pp->idx >= DWAPB_MAX_PORTS) {
|
|
dev_err(dev,
|
|
"missing/invalid port index for port%d\n", i);
|
|
fwnode_handle_put(fwnode);
|
|
return ERR_PTR(-EINVAL);
|
|
}
|
|
|
|
if (fwnode_property_read_u32(fwnode, "snps,nr-gpios",
|
|
&pp->ngpio)) {
|
|
dev_info(dev,
|
|
"failed to get number of gpios for port%d\n",
|
|
i);
|
|
pp->ngpio = 32;
|
|
}
|
|
|
|
/*
|
|
* Only port A can provide interrupts in all configurations of
|
|
* the IP.
|
|
*/
|
|
if (dev->of_node && pp->idx == 0 &&
|
|
fwnode_property_read_bool(fwnode,
|
|
"interrupt-controller")) {
|
|
pp->irq = irq_of_parse_and_map(to_of_node(fwnode), 0);
|
|
if (!pp->irq)
|
|
dev_warn(dev, "no irq for port%d\n", pp->idx);
|
|
}
|
|
|
|
if (has_acpi_companion(dev) && pp->idx == 0)
|
|
pp->irq = platform_get_irq(to_platform_device(dev), 0);
|
|
|
|
pp->irq_shared = false;
|
|
pp->gpio_base = -1;
|
|
}
|
|
|
|
return pdata;
|
|
}
|
|
|
|
static const struct of_device_id dwapb_of_match[] = {
|
|
{ .compatible = "snps,dw-apb-gpio", .data = (void *)0},
|
|
{ .compatible = "apm,xgene-gpio-v2", .data = (void *)GPIO_REG_OFFSET_V2},
|
|
{ /* Sentinel */ }
|
|
};
|
|
MODULE_DEVICE_TABLE(of, dwapb_of_match);
|
|
|
|
static const struct acpi_device_id dwapb_acpi_match[] = {
|
|
{"HISI0181", 0},
|
|
{"APMC0D07", 0},
|
|
{"APMC0D81", GPIO_REG_OFFSET_V2},
|
|
{ }
|
|
};
|
|
MODULE_DEVICE_TABLE(acpi, dwapb_acpi_match);
|
|
|
|
static int dwapb_gpio_probe(struct platform_device *pdev)
|
|
{
|
|
unsigned int i;
|
|
struct resource *res;
|
|
struct dwapb_gpio *gpio;
|
|
int err;
|
|
struct device *dev = &pdev->dev;
|
|
struct dwapb_platform_data *pdata = dev_get_platdata(dev);
|
|
|
|
if (!pdata) {
|
|
pdata = dwapb_gpio_get_pdata(dev);
|
|
if (IS_ERR(pdata))
|
|
return PTR_ERR(pdata);
|
|
}
|
|
|
|
if (!pdata->nports)
|
|
return -ENODEV;
|
|
|
|
gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
|
|
if (!gpio)
|
|
return -ENOMEM;
|
|
|
|
gpio->dev = &pdev->dev;
|
|
gpio->nr_ports = pdata->nports;
|
|
|
|
gpio->ports = devm_kcalloc(&pdev->dev, gpio->nr_ports,
|
|
sizeof(*gpio->ports), GFP_KERNEL);
|
|
if (!gpio->ports)
|
|
return -ENOMEM;
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
gpio->regs = devm_ioremap_resource(&pdev->dev, res);
|
|
if (IS_ERR(gpio->regs))
|
|
return PTR_ERR(gpio->regs);
|
|
|
|
gpio->flags = 0;
|
|
if (dev->of_node) {
|
|
const struct of_device_id *of_devid;
|
|
|
|
of_devid = of_match_device(dwapb_of_match, dev);
|
|
if (of_devid) {
|
|
if (of_devid->data)
|
|
gpio->flags = (uintptr_t)of_devid->data;
|
|
}
|
|
} else if (has_acpi_companion(dev)) {
|
|
const struct acpi_device_id *acpi_id;
|
|
|
|
acpi_id = acpi_match_device(dwapb_acpi_match, dev);
|
|
if (acpi_id) {
|
|
if (acpi_id->driver_data)
|
|
gpio->flags = acpi_id->driver_data;
|
|
}
|
|
}
|
|
|
|
for (i = 0; i < gpio->nr_ports; i++) {
|
|
err = dwapb_gpio_add_port(gpio, &pdata->properties[i], i);
|
|
if (err)
|
|
goto out_unregister;
|
|
}
|
|
platform_set_drvdata(pdev, gpio);
|
|
|
|
return 0;
|
|
|
|
out_unregister:
|
|
dwapb_gpio_unregister(gpio);
|
|
dwapb_irq_teardown(gpio);
|
|
|
|
return err;
|
|
}
|
|
|
|
static int dwapb_gpio_remove(struct platform_device *pdev)
|
|
{
|
|
struct dwapb_gpio *gpio = platform_get_drvdata(pdev);
|
|
|
|
dwapb_gpio_unregister(gpio);
|
|
dwapb_irq_teardown(gpio);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_PM_SLEEP
|
|
static int dwapb_gpio_suspend(struct device *dev)
|
|
{
|
|
struct platform_device *pdev = to_platform_device(dev);
|
|
struct dwapb_gpio *gpio = platform_get_drvdata(pdev);
|
|
struct gpio_chip *gc = &gpio->ports[0].gc;
|
|
unsigned long flags;
|
|
int i;
|
|
|
|
spin_lock_irqsave(&gc->bgpio_lock, flags);
|
|
for (i = 0; i < gpio->nr_ports; i++) {
|
|
unsigned int offset;
|
|
unsigned int idx = gpio->ports[i].idx;
|
|
struct dwapb_context *ctx = gpio->ports[i].ctx;
|
|
|
|
BUG_ON(!ctx);
|
|
|
|
offset = GPIO_SWPORTA_DDR + idx * GPIO_SWPORT_DDR_SIZE;
|
|
ctx->dir = dwapb_read(gpio, offset);
|
|
|
|
offset = GPIO_SWPORTA_DR + idx * GPIO_SWPORT_DR_SIZE;
|
|
ctx->data = dwapb_read(gpio, offset);
|
|
|
|
offset = GPIO_EXT_PORTA + idx * GPIO_EXT_PORT_SIZE;
|
|
ctx->ext = dwapb_read(gpio, offset);
|
|
|
|
/* Only port A can provide interrupts */
|
|
if (idx == 0) {
|
|
ctx->int_mask = dwapb_read(gpio, GPIO_INTMASK);
|
|
ctx->int_en = dwapb_read(gpio, GPIO_INTEN);
|
|
ctx->int_pol = dwapb_read(gpio, GPIO_INT_POLARITY);
|
|
ctx->int_type = dwapb_read(gpio, GPIO_INTTYPE_LEVEL);
|
|
ctx->int_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE);
|
|
|
|
/* Mask out interrupts */
|
|
dwapb_write(gpio, GPIO_INTMASK, 0xffffffff);
|
|
}
|
|
}
|
|
spin_unlock_irqrestore(&gc->bgpio_lock, flags);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int dwapb_gpio_resume(struct device *dev)
|
|
{
|
|
struct platform_device *pdev = to_platform_device(dev);
|
|
struct dwapb_gpio *gpio = platform_get_drvdata(pdev);
|
|
struct gpio_chip *gc = &gpio->ports[0].gc;
|
|
unsigned long flags;
|
|
int i;
|
|
|
|
spin_lock_irqsave(&gc->bgpio_lock, flags);
|
|
for (i = 0; i < gpio->nr_ports; i++) {
|
|
unsigned int offset;
|
|
unsigned int idx = gpio->ports[i].idx;
|
|
struct dwapb_context *ctx = gpio->ports[i].ctx;
|
|
|
|
BUG_ON(!ctx);
|
|
|
|
offset = GPIO_SWPORTA_DR + idx * GPIO_SWPORT_DR_SIZE;
|
|
dwapb_write(gpio, offset, ctx->data);
|
|
|
|
offset = GPIO_SWPORTA_DDR + idx * GPIO_SWPORT_DDR_SIZE;
|
|
dwapb_write(gpio, offset, ctx->dir);
|
|
|
|
offset = GPIO_EXT_PORTA + idx * GPIO_EXT_PORT_SIZE;
|
|
dwapb_write(gpio, offset, ctx->ext);
|
|
|
|
/* Only port A can provide interrupts */
|
|
if (idx == 0) {
|
|
dwapb_write(gpio, GPIO_INTTYPE_LEVEL, ctx->int_type);
|
|
dwapb_write(gpio, GPIO_INT_POLARITY, ctx->int_pol);
|
|
dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, ctx->int_deb);
|
|
dwapb_write(gpio, GPIO_INTEN, ctx->int_en);
|
|
dwapb_write(gpio, GPIO_INTMASK, ctx->int_mask);
|
|
|
|
/* Clear out spurious interrupts */
|
|
dwapb_write(gpio, GPIO_PORTA_EOI, 0xffffffff);
|
|
}
|
|
}
|
|
spin_unlock_irqrestore(&gc->bgpio_lock, flags);
|
|
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
static SIMPLE_DEV_PM_OPS(dwapb_gpio_pm_ops, dwapb_gpio_suspend,
|
|
dwapb_gpio_resume);
|
|
|
|
static struct platform_driver dwapb_gpio_driver = {
|
|
.driver = {
|
|
.name = "gpio-dwapb",
|
|
.pm = &dwapb_gpio_pm_ops,
|
|
.of_match_table = of_match_ptr(dwapb_of_match),
|
|
.acpi_match_table = ACPI_PTR(dwapb_acpi_match),
|
|
},
|
|
.probe = dwapb_gpio_probe,
|
|
.remove = dwapb_gpio_remove,
|
|
};
|
|
|
|
module_platform_driver(dwapb_gpio_driver);
|
|
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_AUTHOR("Jamie Iles");
|
|
MODULE_DESCRIPTION("Synopsys DesignWare APB GPIO driver");
|