forked from Minki/linux
24a07a1241
The ADSP-BF54x was specifically designed to meet the needs of convergent multimedia applications where system performance and cost are essential ingredients. The integration of multimedia, human interface, and connectivity peripherals combined with increased system bandwidth and on-chip memory provides customers a platform to design the most demanding applications. Since now, ADSP-BF54x will be supported in the Linux kernel and bunch of related drivers such as USB OTG, ATAPI, NAND flash controller, LCD framebuffer, sound, touch screen will be submitted later. Please enjoy the show. Signed-off-by: Roy Huang <roy.huang@analog.com> Signed-off-by: Bryan Wu <bryan.wu@analog.com>
751 lines
20 KiB
C
751 lines
20 KiB
C
/*
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* File: arch/blackfin/kernel/bfin_dma_5xx.c
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* Based on:
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* Author:
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*
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* Created:
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* Description: This file contains the simple DMA Implementation for Blackfin
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*
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* Modified:
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* Copyright 2004-2006 Analog Devices Inc.
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*
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* Bugs: Enter bugs at http://blackfin.uclinux.org/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see the file COPYING, or write
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* to the Free Software Foundation, Inc.,
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* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <linux/errno.h>
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#include <linux/module.h>
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#include <linux/sched.h>
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/param.h>
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#include <asm/blackfin.h>
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#include <asm/dma.h>
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#include <asm/cacheflush.h>
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/* Remove unused code not exported by symbol or internally called */
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#define REMOVE_DEAD_CODE
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/**************************************************************************
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* Global Variables
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***************************************************************************/
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static struct dma_channel dma_ch[MAX_BLACKFIN_DMA_CHANNEL];
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/*------------------------------------------------------------------------------
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* Set the Buffer Clear bit in the Configuration register of specific DMA
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* channel. This will stop the descriptor based DMA operation.
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*-----------------------------------------------------------------------------*/
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static void clear_dma_buffer(unsigned int channel)
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{
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dma_ch[channel].regs->cfg |= RESTART;
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SSYNC();
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dma_ch[channel].regs->cfg &= ~RESTART;
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SSYNC();
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}
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static int __init blackfin_dma_init(void)
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{
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int i;
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printk(KERN_INFO "Blackfin DMA Controller\n");
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for (i = 0; i < MAX_BLACKFIN_DMA_CHANNEL; i++) {
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dma_ch[i].chan_status = DMA_CHANNEL_FREE;
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dma_ch[i].regs = base_addr[i];
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mutex_init(&(dma_ch[i].dmalock));
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}
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/* Mark MEMDMA Channel 0 as requested since we're using it internally */
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dma_ch[CH_MEM_STREAM0_DEST].chan_status = DMA_CHANNEL_REQUESTED;
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dma_ch[CH_MEM_STREAM0_SRC].chan_status = DMA_CHANNEL_REQUESTED;
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return 0;
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}
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arch_initcall(blackfin_dma_init);
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/*------------------------------------------------------------------------------
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* Request the specific DMA channel from the system.
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*-----------------------------------------------------------------------------*/
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int request_dma(unsigned int channel, char *device_id)
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{
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pr_debug("request_dma() : BEGIN \n");
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mutex_lock(&(dma_ch[channel].dmalock));
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if ((dma_ch[channel].chan_status == DMA_CHANNEL_REQUESTED)
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|| (dma_ch[channel].chan_status == DMA_CHANNEL_ENABLED)) {
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mutex_unlock(&(dma_ch[channel].dmalock));
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pr_debug("DMA CHANNEL IN USE \n");
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return -EBUSY;
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} else {
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dma_ch[channel].chan_status = DMA_CHANNEL_REQUESTED;
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pr_debug("DMA CHANNEL IS ALLOCATED \n");
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}
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mutex_unlock(&(dma_ch[channel].dmalock));
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dma_ch[channel].device_id = device_id;
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dma_ch[channel].irq_callback = NULL;
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/* This is to be enabled by putting a restriction -
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* you have to request DMA, before doing any operations on
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* descriptor/channel
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*/
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pr_debug("request_dma() : END \n");
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return channel;
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}
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EXPORT_SYMBOL(request_dma);
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int set_dma_callback(unsigned int channel, dma_interrupt_t callback, void *data)
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{
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int ret_irq = 0;
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BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
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&& channel < MAX_BLACKFIN_DMA_CHANNEL));
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if (callback != NULL) {
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int ret_val;
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ret_irq = channel2irq(channel);
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dma_ch[channel].data = data;
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ret_val =
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request_irq(ret_irq, (void *)callback, IRQF_DISABLED,
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dma_ch[channel].device_id, data);
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if (ret_val) {
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printk(KERN_NOTICE
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"Request irq in DMA engine failed.\n");
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return -EPERM;
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}
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dma_ch[channel].irq_callback = callback;
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}
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return 0;
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}
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EXPORT_SYMBOL(set_dma_callback);
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void free_dma(unsigned int channel)
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{
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int ret_irq;
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pr_debug("freedma() : BEGIN \n");
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BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
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&& channel < MAX_BLACKFIN_DMA_CHANNEL));
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/* Halt the DMA */
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disable_dma(channel);
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clear_dma_buffer(channel);
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if (dma_ch[channel].irq_callback != NULL) {
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ret_irq = channel2irq(channel);
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free_irq(ret_irq, dma_ch[channel].data);
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}
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/* Clear the DMA Variable in the Channel */
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mutex_lock(&(dma_ch[channel].dmalock));
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dma_ch[channel].chan_status = DMA_CHANNEL_FREE;
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mutex_unlock(&(dma_ch[channel].dmalock));
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pr_debug("freedma() : END \n");
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}
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EXPORT_SYMBOL(free_dma);
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void dma_enable_irq(unsigned int channel)
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{
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int ret_irq;
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pr_debug("dma_enable_irq() : BEGIN \n");
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BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
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&& channel < MAX_BLACKFIN_DMA_CHANNEL));
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ret_irq = channel2irq(channel);
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enable_irq(ret_irq);
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}
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EXPORT_SYMBOL(dma_enable_irq);
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void dma_disable_irq(unsigned int channel)
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{
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int ret_irq;
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pr_debug("dma_disable_irq() : BEGIN \n");
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BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
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&& channel < MAX_BLACKFIN_DMA_CHANNEL));
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ret_irq = channel2irq(channel);
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disable_irq(ret_irq);
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}
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EXPORT_SYMBOL(dma_disable_irq);
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int dma_channel_active(unsigned int channel)
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{
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if (dma_ch[channel].chan_status == DMA_CHANNEL_FREE) {
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return 0;
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} else {
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return 1;
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}
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}
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EXPORT_SYMBOL(dma_channel_active);
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/*------------------------------------------------------------------------------
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* stop the specific DMA channel.
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*-----------------------------------------------------------------------------*/
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void disable_dma(unsigned int channel)
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{
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pr_debug("stop_dma() : BEGIN \n");
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BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
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&& channel < MAX_BLACKFIN_DMA_CHANNEL));
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dma_ch[channel].regs->cfg &= ~DMAEN; /* Clean the enable bit */
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SSYNC();
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dma_ch[channel].chan_status = DMA_CHANNEL_REQUESTED;
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/* Needs to be enabled Later */
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pr_debug("stop_dma() : END \n");
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return;
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}
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EXPORT_SYMBOL(disable_dma);
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void enable_dma(unsigned int channel)
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{
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pr_debug("enable_dma() : BEGIN \n");
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BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
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&& channel < MAX_BLACKFIN_DMA_CHANNEL));
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dma_ch[channel].chan_status = DMA_CHANNEL_ENABLED;
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dma_ch[channel].regs->curr_x_count = 0;
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dma_ch[channel].regs->curr_y_count = 0;
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dma_ch[channel].regs->cfg |= DMAEN; /* Set the enable bit */
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SSYNC();
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pr_debug("enable_dma() : END \n");
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return;
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}
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EXPORT_SYMBOL(enable_dma);
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/*------------------------------------------------------------------------------
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* Set the Start Address register for the specific DMA channel
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* This function can be used for register based DMA,
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* to setup the start address
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* addr: Starting address of the DMA Data to be transferred.
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*-----------------------------------------------------------------------------*/
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void set_dma_start_addr(unsigned int channel, unsigned long addr)
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{
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pr_debug("set_dma_start_addr() : BEGIN \n");
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BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
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&& channel < MAX_BLACKFIN_DMA_CHANNEL));
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dma_ch[channel].regs->start_addr = addr;
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SSYNC();
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pr_debug("set_dma_start_addr() : END\n");
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}
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EXPORT_SYMBOL(set_dma_start_addr);
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void set_dma_next_desc_addr(unsigned int channel, unsigned long addr)
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{
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pr_debug("set_dma_next_desc_addr() : BEGIN \n");
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BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
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&& channel < MAX_BLACKFIN_DMA_CHANNEL));
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dma_ch[channel].regs->next_desc_ptr = addr;
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SSYNC();
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pr_debug("set_dma_start_addr() : END\n");
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}
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EXPORT_SYMBOL(set_dma_next_desc_addr);
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void set_dma_x_count(unsigned int channel, unsigned short x_count)
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{
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BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
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&& channel < MAX_BLACKFIN_DMA_CHANNEL));
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dma_ch[channel].regs->x_count = x_count;
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SSYNC();
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}
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EXPORT_SYMBOL(set_dma_x_count);
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void set_dma_y_count(unsigned int channel, unsigned short y_count)
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{
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BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
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&& channel < MAX_BLACKFIN_DMA_CHANNEL));
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dma_ch[channel].regs->y_count = y_count;
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SSYNC();
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}
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EXPORT_SYMBOL(set_dma_y_count);
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void set_dma_x_modify(unsigned int channel, short x_modify)
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{
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BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
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&& channel < MAX_BLACKFIN_DMA_CHANNEL));
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dma_ch[channel].regs->x_modify = x_modify;
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SSYNC();
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}
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EXPORT_SYMBOL(set_dma_x_modify);
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void set_dma_y_modify(unsigned int channel, short y_modify)
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{
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BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
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&& channel < MAX_BLACKFIN_DMA_CHANNEL));
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dma_ch[channel].regs->y_modify = y_modify;
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SSYNC();
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}
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EXPORT_SYMBOL(set_dma_y_modify);
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void set_dma_config(unsigned int channel, unsigned short config)
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{
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BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
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&& channel < MAX_BLACKFIN_DMA_CHANNEL));
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dma_ch[channel].regs->cfg = config;
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SSYNC();
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}
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EXPORT_SYMBOL(set_dma_config);
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unsigned short
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set_bfin_dma_config(char direction, char flow_mode,
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char intr_mode, char dma_mode, char width)
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{
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unsigned short config;
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config =
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((direction << 1) | (width << 2) | (dma_mode << 4) |
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(intr_mode << 6) | (flow_mode << 12) | RESTART);
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return config;
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}
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EXPORT_SYMBOL(set_bfin_dma_config);
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void set_dma_sg(unsigned int channel, struct dmasg * sg, int nr_sg)
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{
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BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
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&& channel < MAX_BLACKFIN_DMA_CHANNEL));
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dma_ch[channel].regs->cfg |= ((nr_sg & 0x0F) << 8);
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dma_ch[channel].regs->next_desc_ptr = (unsigned int)sg;
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SSYNC();
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}
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EXPORT_SYMBOL(set_dma_sg);
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/*------------------------------------------------------------------------------
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* Get the DMA status of a specific DMA channel from the system.
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*-----------------------------------------------------------------------------*/
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unsigned short get_dma_curr_irqstat(unsigned int channel)
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{
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BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
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&& channel < MAX_BLACKFIN_DMA_CHANNEL));
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return dma_ch[channel].regs->irq_status;
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}
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EXPORT_SYMBOL(get_dma_curr_irqstat);
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/*------------------------------------------------------------------------------
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* Clear the DMA_DONE bit in DMA status. Stop the DMA completion interrupt.
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*-----------------------------------------------------------------------------*/
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void clear_dma_irqstat(unsigned int channel)
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{
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BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
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&& channel < MAX_BLACKFIN_DMA_CHANNEL));
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dma_ch[channel].regs->irq_status |= 3;
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}
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EXPORT_SYMBOL(clear_dma_irqstat);
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/*------------------------------------------------------------------------------
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* Get current DMA xcount of a specific DMA channel from the system.
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*-----------------------------------------------------------------------------*/
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unsigned short get_dma_curr_xcount(unsigned int channel)
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{
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BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
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&& channel < MAX_BLACKFIN_DMA_CHANNEL));
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return dma_ch[channel].regs->curr_x_count;
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}
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EXPORT_SYMBOL(get_dma_curr_xcount);
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/*------------------------------------------------------------------------------
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* Get current DMA ycount of a specific DMA channel from the system.
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*-----------------------------------------------------------------------------*/
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unsigned short get_dma_curr_ycount(unsigned int channel)
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{
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BUG_ON(!(dma_ch[channel].chan_status != DMA_CHANNEL_FREE
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&& channel < MAX_BLACKFIN_DMA_CHANNEL));
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return dma_ch[channel].regs->curr_y_count;
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}
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EXPORT_SYMBOL(get_dma_curr_ycount);
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static void *__dma_memcpy(void *dest, const void *src, size_t size)
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{
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int direction; /* 1 - address decrease, 0 - address increase */
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int flag_align; /* 1 - address aligned, 0 - address unaligned */
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int flag_2D; /* 1 - 2D DMA needed, 0 - 1D DMA needed */
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unsigned long flags;
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if (size <= 0)
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return NULL;
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local_irq_save(flags);
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if ((unsigned long)src < memory_end)
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blackfin_dcache_flush_range((unsigned int)src,
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(unsigned int)(src + size));
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bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
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if ((unsigned long)src < (unsigned long)dest)
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direction = 1;
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else
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direction = 0;
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if ((((unsigned long)dest % 2) == 0) && (((unsigned long)src % 2) == 0)
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&& ((size % 2) == 0))
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flag_align = 1;
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else
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flag_align = 0;
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if (size > 0x10000) /* size > 64K */
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flag_2D = 1;
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else
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flag_2D = 0;
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/* Setup destination and source start address */
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if (direction) {
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if (flag_align) {
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bfin_write_MDMA_D0_START_ADDR(dest + size - 2);
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bfin_write_MDMA_S0_START_ADDR(src + size - 2);
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} else {
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bfin_write_MDMA_D0_START_ADDR(dest + size - 1);
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bfin_write_MDMA_S0_START_ADDR(src + size - 1);
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}
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} else {
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bfin_write_MDMA_D0_START_ADDR(dest);
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bfin_write_MDMA_S0_START_ADDR(src);
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}
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/* Setup destination and source xcount */
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if (flag_2D) {
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if (flag_align) {
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bfin_write_MDMA_D0_X_COUNT(1024 / 2);
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bfin_write_MDMA_S0_X_COUNT(1024 / 2);
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} else {
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bfin_write_MDMA_D0_X_COUNT(1024);
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bfin_write_MDMA_S0_X_COUNT(1024);
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}
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bfin_write_MDMA_D0_Y_COUNT(size >> 10);
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bfin_write_MDMA_S0_Y_COUNT(size >> 10);
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} else {
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if (flag_align) {
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bfin_write_MDMA_D0_X_COUNT(size / 2);
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bfin_write_MDMA_S0_X_COUNT(size / 2);
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} else {
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bfin_write_MDMA_D0_X_COUNT(size);
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bfin_write_MDMA_S0_X_COUNT(size);
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}
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}
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/* Setup destination and source xmodify and ymodify */
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if (direction) {
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if (flag_align) {
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bfin_write_MDMA_D0_X_MODIFY(-2);
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bfin_write_MDMA_S0_X_MODIFY(-2);
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if (flag_2D) {
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bfin_write_MDMA_D0_Y_MODIFY(-2);
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bfin_write_MDMA_S0_Y_MODIFY(-2);
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}
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} else {
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bfin_write_MDMA_D0_X_MODIFY(-1);
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bfin_write_MDMA_S0_X_MODIFY(-1);
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if (flag_2D) {
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bfin_write_MDMA_D0_Y_MODIFY(-1);
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bfin_write_MDMA_S0_Y_MODIFY(-1);
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}
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}
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} else {
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if (flag_align) {
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bfin_write_MDMA_D0_X_MODIFY(2);
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bfin_write_MDMA_S0_X_MODIFY(2);
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if (flag_2D) {
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bfin_write_MDMA_D0_Y_MODIFY(2);
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bfin_write_MDMA_S0_Y_MODIFY(2);
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}
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} else {
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bfin_write_MDMA_D0_X_MODIFY(1);
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bfin_write_MDMA_S0_X_MODIFY(1);
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if (flag_2D) {
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bfin_write_MDMA_D0_Y_MODIFY(1);
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bfin_write_MDMA_S0_Y_MODIFY(1);
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}
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}
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}
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/* Enable source DMA */
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if (flag_2D) {
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if (flag_align) {
|
|
bfin_write_MDMA_S0_CONFIG(DMAEN | DMA2D | WDSIZE_16);
|
|
bfin_write_MDMA_D0_CONFIG(WNR | DI_EN | DMAEN | DMA2D | WDSIZE_16);
|
|
} else {
|
|
bfin_write_MDMA_S0_CONFIG(DMAEN | DMA2D);
|
|
bfin_write_MDMA_D0_CONFIG(WNR | DI_EN | DMAEN | DMA2D);
|
|
}
|
|
} else {
|
|
if (flag_align) {
|
|
bfin_write_MDMA_S0_CONFIG(DMAEN | WDSIZE_16);
|
|
bfin_write_MDMA_D0_CONFIG(WNR | DI_EN | DMAEN | WDSIZE_16);
|
|
} else {
|
|
bfin_write_MDMA_S0_CONFIG(DMAEN);
|
|
bfin_write_MDMA_D0_CONFIG(WNR | DI_EN | DMAEN);
|
|
}
|
|
}
|
|
|
|
while (!(bfin_read_MDMA_D0_IRQ_STATUS() & DMA_DONE))
|
|
;
|
|
|
|
bfin_write_MDMA_D0_IRQ_STATUS(bfin_read_MDMA_D0_IRQ_STATUS() |
|
|
(DMA_DONE | DMA_ERR));
|
|
|
|
bfin_write_MDMA_S0_CONFIG(0);
|
|
bfin_write_MDMA_D0_CONFIG(0);
|
|
|
|
if ((unsigned long)dest < memory_end)
|
|
blackfin_dcache_invalidate_range((unsigned int)dest,
|
|
(unsigned int)(dest + size));
|
|
local_irq_restore(flags);
|
|
|
|
return dest;
|
|
}
|
|
|
|
void *dma_memcpy(void *dest, const void *src, size_t size)
|
|
{
|
|
size_t bulk;
|
|
size_t rest;
|
|
void * addr;
|
|
|
|
bulk = (size >> 16) << 16;
|
|
rest = size - bulk;
|
|
if (bulk)
|
|
__dma_memcpy(dest, src, bulk);
|
|
addr = __dma_memcpy(dest+bulk, src+bulk, rest);
|
|
return addr;
|
|
}
|
|
|
|
EXPORT_SYMBOL(dma_memcpy);
|
|
|
|
void *safe_dma_memcpy(void *dest, const void *src, size_t size)
|
|
{
|
|
void *addr;
|
|
addr = dma_memcpy(dest, src, size);
|
|
return addr;
|
|
}
|
|
EXPORT_SYMBOL(safe_dma_memcpy);
|
|
|
|
void dma_outsb(void __iomem *addr, const void *buf, unsigned short len)
|
|
{
|
|
|
|
unsigned long flags;
|
|
|
|
local_irq_save(flags);
|
|
|
|
blackfin_dcache_flush_range((unsigned int)buf,(unsigned int)(buf) + len);
|
|
|
|
bfin_write_MDMA_D0_START_ADDR(addr);
|
|
bfin_write_MDMA_D0_X_COUNT(len);
|
|
bfin_write_MDMA_D0_X_MODIFY(0);
|
|
bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
|
|
|
|
bfin_write_MDMA_S0_START_ADDR(buf);
|
|
bfin_write_MDMA_S0_X_COUNT(len);
|
|
bfin_write_MDMA_S0_X_MODIFY(1);
|
|
bfin_write_MDMA_S0_IRQ_STATUS(DMA_DONE | DMA_ERR);
|
|
|
|
bfin_write_MDMA_S0_CONFIG(DMAEN | WDSIZE_8);
|
|
bfin_write_MDMA_D0_CONFIG(WNR | DI_EN | DMAEN | WDSIZE_8);
|
|
|
|
while (!(bfin_read_MDMA_D0_IRQ_STATUS() & DMA_DONE));
|
|
|
|
bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
|
|
|
|
bfin_write_MDMA_S0_CONFIG(0);
|
|
bfin_write_MDMA_D0_CONFIG(0);
|
|
local_irq_restore(flags);
|
|
|
|
}
|
|
EXPORT_SYMBOL(dma_outsb);
|
|
|
|
|
|
void dma_insb(const void __iomem *addr, void *buf, unsigned short len)
|
|
{
|
|
unsigned long flags;
|
|
|
|
local_irq_save(flags);
|
|
bfin_write_MDMA_D0_START_ADDR(buf);
|
|
bfin_write_MDMA_D0_X_COUNT(len);
|
|
bfin_write_MDMA_D0_X_MODIFY(1);
|
|
bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
|
|
|
|
bfin_write_MDMA_S0_START_ADDR(addr);
|
|
bfin_write_MDMA_S0_X_COUNT(len);
|
|
bfin_write_MDMA_S0_X_MODIFY(0);
|
|
bfin_write_MDMA_S0_IRQ_STATUS(DMA_DONE | DMA_ERR);
|
|
|
|
bfin_write_MDMA_S0_CONFIG(DMAEN | WDSIZE_8);
|
|
bfin_write_MDMA_D0_CONFIG(WNR | DI_EN | DMAEN | WDSIZE_8);
|
|
|
|
blackfin_dcache_invalidate_range((unsigned int)buf, (unsigned int)(buf) + len);
|
|
|
|
while (!(bfin_read_MDMA_D0_IRQ_STATUS() & DMA_DONE));
|
|
|
|
bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
|
|
|
|
bfin_write_MDMA_S0_CONFIG(0);
|
|
bfin_write_MDMA_D0_CONFIG(0);
|
|
local_irq_restore(flags);
|
|
|
|
}
|
|
EXPORT_SYMBOL(dma_insb);
|
|
|
|
void dma_outsw(void __iomem *addr, const void *buf, unsigned short len)
|
|
{
|
|
unsigned long flags;
|
|
|
|
local_irq_save(flags);
|
|
|
|
blackfin_dcache_flush_range((unsigned int)buf,(unsigned int)(buf) + len);
|
|
|
|
bfin_write_MDMA_D0_START_ADDR(addr);
|
|
bfin_write_MDMA_D0_X_COUNT(len);
|
|
bfin_write_MDMA_D0_X_MODIFY(0);
|
|
bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
|
|
|
|
bfin_write_MDMA_S0_START_ADDR(buf);
|
|
bfin_write_MDMA_S0_X_COUNT(len);
|
|
bfin_write_MDMA_S0_X_MODIFY(2);
|
|
bfin_write_MDMA_S0_IRQ_STATUS(DMA_DONE | DMA_ERR);
|
|
|
|
bfin_write_MDMA_S0_CONFIG(DMAEN | WDSIZE_16);
|
|
bfin_write_MDMA_D0_CONFIG(WNR | DI_EN | DMAEN | WDSIZE_16);
|
|
|
|
while (!(bfin_read_MDMA_D0_IRQ_STATUS() & DMA_DONE));
|
|
|
|
bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
|
|
|
|
bfin_write_MDMA_S0_CONFIG(0);
|
|
bfin_write_MDMA_D0_CONFIG(0);
|
|
local_irq_restore(flags);
|
|
|
|
}
|
|
EXPORT_SYMBOL(dma_outsw);
|
|
|
|
void dma_insw(const void __iomem *addr, void *buf, unsigned short len)
|
|
{
|
|
unsigned long flags;
|
|
|
|
local_irq_save(flags);
|
|
|
|
bfin_write_MDMA_D0_START_ADDR(buf);
|
|
bfin_write_MDMA_D0_X_COUNT(len);
|
|
bfin_write_MDMA_D0_X_MODIFY(2);
|
|
bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
|
|
|
|
bfin_write_MDMA_S0_START_ADDR(addr);
|
|
bfin_write_MDMA_S0_X_COUNT(len);
|
|
bfin_write_MDMA_S0_X_MODIFY(0);
|
|
bfin_write_MDMA_S0_IRQ_STATUS(DMA_DONE | DMA_ERR);
|
|
|
|
bfin_write_MDMA_S0_CONFIG(DMAEN | WDSIZE_16);
|
|
bfin_write_MDMA_D0_CONFIG(WNR | DI_EN | DMAEN | WDSIZE_16);
|
|
|
|
blackfin_dcache_invalidate_range((unsigned int)buf, (unsigned int)(buf) + len);
|
|
|
|
while (!(bfin_read_MDMA_D0_IRQ_STATUS() & DMA_DONE));
|
|
|
|
bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
|
|
|
|
bfin_write_MDMA_S0_CONFIG(0);
|
|
bfin_write_MDMA_D0_CONFIG(0);
|
|
local_irq_restore(flags);
|
|
|
|
}
|
|
EXPORT_SYMBOL(dma_insw);
|
|
|
|
void dma_outsl(void __iomem *addr, const void *buf, unsigned short len)
|
|
{
|
|
unsigned long flags;
|
|
|
|
local_irq_save(flags);
|
|
|
|
blackfin_dcache_flush_range((unsigned int)buf,(unsigned int)(buf) + len);
|
|
|
|
bfin_write_MDMA_D0_START_ADDR(addr);
|
|
bfin_write_MDMA_D0_X_COUNT(len);
|
|
bfin_write_MDMA_D0_X_MODIFY(0);
|
|
bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
|
|
|
|
bfin_write_MDMA_S0_START_ADDR(buf);
|
|
bfin_write_MDMA_S0_X_COUNT(len);
|
|
bfin_write_MDMA_S0_X_MODIFY(4);
|
|
bfin_write_MDMA_S0_IRQ_STATUS(DMA_DONE | DMA_ERR);
|
|
|
|
bfin_write_MDMA_S0_CONFIG(DMAEN | WDSIZE_32);
|
|
bfin_write_MDMA_D0_CONFIG(WNR | DI_EN | DMAEN | WDSIZE_32);
|
|
|
|
while (!(bfin_read_MDMA_D0_IRQ_STATUS() & DMA_DONE));
|
|
|
|
bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
|
|
|
|
bfin_write_MDMA_S0_CONFIG(0);
|
|
bfin_write_MDMA_D0_CONFIG(0);
|
|
local_irq_restore(flags);
|
|
|
|
}
|
|
EXPORT_SYMBOL(dma_outsl);
|
|
|
|
void dma_insl(const void __iomem *addr, void *buf, unsigned short len)
|
|
{
|
|
unsigned long flags;
|
|
|
|
local_irq_save(flags);
|
|
|
|
bfin_write_MDMA_D0_START_ADDR(buf);
|
|
bfin_write_MDMA_D0_X_COUNT(len);
|
|
bfin_write_MDMA_D0_X_MODIFY(4);
|
|
bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
|
|
|
|
bfin_write_MDMA_S0_START_ADDR(addr);
|
|
bfin_write_MDMA_S0_X_COUNT(len);
|
|
bfin_write_MDMA_S0_X_MODIFY(0);
|
|
bfin_write_MDMA_S0_IRQ_STATUS(DMA_DONE | DMA_ERR);
|
|
|
|
bfin_write_MDMA_S0_CONFIG(DMAEN | WDSIZE_32);
|
|
bfin_write_MDMA_D0_CONFIG(WNR | DI_EN | DMAEN | WDSIZE_32);
|
|
|
|
blackfin_dcache_invalidate_range((unsigned int)buf, (unsigned int)(buf) + len);
|
|
|
|
while (!(bfin_read_MDMA_D0_IRQ_STATUS() & DMA_DONE));
|
|
|
|
bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
|
|
|
|
bfin_write_MDMA_S0_CONFIG(0);
|
|
bfin_write_MDMA_D0_CONFIG(0);
|
|
local_irq_restore(flags);
|
|
|
|
}
|
|
EXPORT_SYMBOL(dma_insl);
|