Sebastian Hesselbarth 668e84b20f mmc: sdhci-pxav3: Respect MMC_DDR52 timing on uhs signaling ... commit bb8175a8aa ("mmc: sdhci: clarify DDR timing mode between SD-UHS and eMMC") added MMC_DDR52 as eMMC's DDR mode to be distinguished from SD-UHS. While the differentation may be useful, pxav3 SDHCI controller lacks a corresponding check in its custom .set_uhs_signaling callback for MMC_DDR52. This patch adds a new switch case for MMC_TIMING_MMC_DDR52 to MMC_TIMING_UHS_DDR50 case. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>		2014-11-10 12:40:30 +01:00
..
card	mmc: block: add newline to sysfs display of force_ro	2014-11-10 12:40:24 +01:00
core	mmc: core: fix prepared requests while doing bkops	2014-11-10 12:40:28 +01:00
host	mmc: sdhci-pxav3: Respect MMC_DDR52 timing on uhs signaling	2014-11-10 12:40:30 +01:00
Kconfig
Makefile	mmc: sdhci-pci: add platform data	2012-01-11 23:58:47 -05:00