forked from Minki/linux
43d24e76b6
This patch implements a device-tree-only CPU DAI driver for Freescale ESAI
controller that supports:
- 12 channels playback and 8 channels record.
[ Some of the inner transmitters and receivers are sharing same group of
pins. So the maxmium 12 output or 8 input channels are only valid if
there is no pin conflict occurring to it. ]
- Independent (asynchronous mode) or shared (synchronous mode) transmit and
receive sections with separate or shared internal/external clocks and frame
syncs, operating in Master or Slave mode.
[ Current ALSA seems not to allow CPU DAI drivers to configure DAI format
separately for PLAYBACK and CAPTURE. So this first version only supports
the case that uses the same DAI format for both directions. ]
- Various DAI formats: I2S, Left-Justified, Right-Justified, DSP-A and DSP-B.
- Programmable word length (8, 16, 20 or 24bits)
- Flexible selection between system clock or external oscillator as input
clock source, programmable internal clock divider and frame sync generation.
Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
51 lines
1.7 KiB
Plaintext
51 lines
1.7 KiB
Plaintext
Freescale Enhanced Serial Audio Interface (ESAI) Controller
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The Enhanced Serial Audio Interface (ESAI) provides a full-duplex serial port
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for serial communication with a variety of serial devices, including industry
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standard codecs, Sony/Phillips Digital Interface (S/PDIF) transceivers, and
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other DSPs. It has up to six transmitters and four receivers.
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Required properties:
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- compatible : Compatible list, must contain "fsl,imx35-esai".
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- reg : Offset and length of the register set for the device.
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- interrupts : Contains the spdif interrupt.
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- dmas : Generic dma devicetree binding as described in
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Documentation/devicetree/bindings/dma/dma.txt.
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- dma-names : Two dmas have to be defined, "tx" and "rx".
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- clocks: Contains an entry for each entry in clock-names.
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- clock-names : Includes the following entries:
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"core" The core clock used to access registers
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"extal" The esai baud clock for esai controller used to derive
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HCK, SCK and FS.
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"fsys" The system clock derived from ahb clock used to derive
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HCK, SCK and FS.
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- fsl,fifo-depth: The number of elements in the transmit and receive FIFOs.
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This number is the maximum allowed value for TFCR[TFWM] or RFCR[RFWM].
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- fsl,esai-synchronous: This is a boolean property. If present, indicating
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that ESAI would work in the synchronous mode, which means all the settings
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for Receiving would be duplicated from Transmition related registers.
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Example:
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esai: esai@02024000 {
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compatible = "fsl,imx35-esai";
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reg = <0x02024000 0x4000>;
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interrupts = <0 51 0x04>;
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clocks = <&clks 208>, <&clks 118>, <&clks 208>;
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clock-names = "core", "extal", "fsys";
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dmas = <&sdma 23 21 0>, <&sdma 24 21 0>;
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dma-names = "rx", "tx";
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fsl,fifo-depth = <128>;
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fsl,esai-synchronous;
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status = "disabled";
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};
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