169 lines
5.2 KiB
C
169 lines
5.2 KiB
C
/*
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* Copyright 2012 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#include "nv50.h"
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#include "outpdp.h"
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#include <subdev/timer.h>
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static inline u32
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g94_sor_soff(struct nvkm_output_dp *outp)
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{
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return (ffs(outp->base.info.or) - 1) * 0x800;
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}
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static inline u32
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g94_sor_loff(struct nvkm_output_dp *outp)
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{
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return g94_sor_soff(outp) + !(outp->base.info.sorconf.link & 1) * 0x80;
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}
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/*******************************************************************************
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* TMDS/LVDS
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******************************************************************************/
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static const struct nvkm_output_func
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g94_sor_output_func = {
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};
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int
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g94_sor_output_new(struct nvkm_disp *disp, int index,
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struct dcb_output *dcbE, struct nvkm_output **poutp)
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{
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return nvkm_output_new_(&g94_sor_output_func, disp,
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index, dcbE, poutp);
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}
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/*******************************************************************************
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* DisplayPort
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******************************************************************************/
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u32
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g94_sor_dp_lane_map(struct nvkm_device *device, u8 lane)
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{
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static const u8 gm100[] = { 0, 8, 16, 24 };
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static const u8 mcp89[] = { 24, 16, 8, 0 }; /* thanks, apple.. */
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static const u8 g94[] = { 16, 8, 0, 24 };
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if (device->chipset >= 0x110)
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return gm100[lane];
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if (device->chipset == 0xaf)
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return mcp89[lane];
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return g94[lane];
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}
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static int
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g94_sor_dp_pattern(struct nvkm_output_dp *outp, int pattern)
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{
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struct nvkm_device *device = outp->base.disp->engine.subdev.device;
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const u32 loff = g94_sor_loff(outp);
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nvkm_mask(device, 0x61c10c + loff, 0x0f000000, pattern << 24);
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return 0;
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}
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int
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g94_sor_dp_lnk_pwr(struct nvkm_output_dp *outp, int nr)
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{
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struct nvkm_device *device = outp->base.disp->engine.subdev.device;
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const u32 soff = g94_sor_soff(outp);
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const u32 loff = g94_sor_loff(outp);
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u32 mask = 0, i;
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for (i = 0; i < nr; i++)
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mask |= 1 << (g94_sor_dp_lane_map(device, i) >> 3);
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nvkm_mask(device, 0x61c130 + loff, 0x0000000f, mask);
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nvkm_mask(device, 0x61c034 + soff, 0x80000000, 0x80000000);
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nvkm_msec(device, 2000,
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if (!(nvkm_rd32(device, 0x61c034 + soff) & 0x80000000))
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break;
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);
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return 0;
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}
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static int
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g94_sor_dp_lnk_ctl(struct nvkm_output_dp *outp, int nr, int bw, bool ef)
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{
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struct nvkm_device *device = outp->base.disp->engine.subdev.device;
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const u32 soff = g94_sor_soff(outp);
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const u32 loff = g94_sor_loff(outp);
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u32 dpctrl = 0x00000000;
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u32 clksor = 0x00000000;
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dpctrl |= ((1 << nr) - 1) << 16;
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if (ef)
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dpctrl |= 0x00004000;
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if (bw > 0x06)
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clksor |= 0x00040000;
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nvkm_mask(device, 0x614300 + soff, 0x000c0000, clksor);
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nvkm_mask(device, 0x61c10c + loff, 0x001f4000, dpctrl);
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return 0;
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}
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static int
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g94_sor_dp_drv_ctl(struct nvkm_output_dp *outp, int ln, int vs, int pe, int pc)
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{
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struct nvkm_device *device = outp->base.disp->engine.subdev.device;
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struct nvkm_bios *bios = device->bios;
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const u32 shift = g94_sor_dp_lane_map(device, ln);
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const u32 loff = g94_sor_loff(outp);
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u32 addr, data[3];
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u8 ver, hdr, cnt, len;
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struct nvbios_dpout info;
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struct nvbios_dpcfg ocfg;
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addr = nvbios_dpout_match(bios, outp->base.info.hasht,
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outp->base.info.hashm,
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&ver, &hdr, &cnt, &len, &info);
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if (!addr)
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return -ENODEV;
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addr = nvbios_dpcfg_match(bios, addr, 0, vs, pe,
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&ver, &hdr, &cnt, &len, &ocfg);
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if (!addr)
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return -EINVAL;
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data[0] = nvkm_rd32(device, 0x61c118 + loff) & ~(0x000000ff << shift);
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data[1] = nvkm_rd32(device, 0x61c120 + loff) & ~(0x000000ff << shift);
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data[2] = nvkm_rd32(device, 0x61c130 + loff);
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if ((data[2] & 0x0000ff00) < (ocfg.tx_pu << 8) || ln == 0)
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data[2] = (data[2] & ~0x0000ff00) | (ocfg.tx_pu << 8);
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nvkm_wr32(device, 0x61c118 + loff, data[0] | (ocfg.dc << shift));
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nvkm_wr32(device, 0x61c120 + loff, data[1] | (ocfg.pe << shift));
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nvkm_wr32(device, 0x61c130 + loff, data[2]);
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return 0;
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}
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static const struct nvkm_output_dp_func
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g94_sor_dp_func = {
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.pattern = g94_sor_dp_pattern,
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.lnk_pwr = g94_sor_dp_lnk_pwr,
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.lnk_ctl = g94_sor_dp_lnk_ctl,
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.drv_ctl = g94_sor_dp_drv_ctl,
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};
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int
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g94_sor_dp_new(struct nvkm_disp *disp, int index, struct dcb_output *dcbE,
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struct nvkm_output **poutp)
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{
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return nvkm_output_dp_new_(&g94_sor_dp_func, disp, index, dcbE, poutp);
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}
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