forked from Minki/linux
0a32241d8b
Will be required by future work. Make the API change now to catch any (but hopefully none) unexpected fallout. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
404 lines
11 KiB
C
404 lines
11 KiB
C
/*
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* Copyright 2010 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#include <drm/drmP.h>
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#include "nouveau_drm.h"
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#include "nouveau_dma.h"
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#include "nv50_display.h"
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#include <core/gpuobj.h>
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#include <subdev/timer.h>
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#include <subdev/fb.h>
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static u32
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nv50_evo_rd32(struct nouveau_object *object, u64 addr)
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{
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void __iomem *iomem = object->oclass->ofuncs->rd08;
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return ioread32_native(iomem + addr);
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}
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static void
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nv50_evo_wr32(struct nouveau_object *object, u64 addr, u32 data)
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{
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void __iomem *iomem = object->oclass->ofuncs->rd08;
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iowrite32_native(data, iomem + addr);
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}
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static void
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nv50_evo_channel_del(struct nouveau_channel **pevo)
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{
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struct nouveau_channel *evo = *pevo;
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if (!evo)
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return;
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*pevo = NULL;
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nouveau_bo_unmap(evo->push.buffer);
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nouveau_bo_ref(NULL, &evo->push.buffer);
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if (evo->object)
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iounmap(evo->object->oclass->ofuncs);
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kfree(evo);
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}
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int
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nv50_evo_dmaobj_new(struct nouveau_channel *evo, u32 handle, u32 memtype,
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u64 base, u64 size, struct nouveau_gpuobj **pobj)
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{
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struct drm_device *dev = evo->fence;
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struct nouveau_drm *drm = nouveau_drm(dev);
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struct nv50_display *disp = nv50_display(dev);
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u32 dmao = disp->dmao;
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u32 hash = disp->hash;
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u32 flags5;
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if (nv_device(drm->device)->chipset < 0xc0) {
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/* not supported on 0x50, specified in format mthd */
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if (nv_device(drm->device)->chipset == 0x50)
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memtype = 0;
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flags5 = 0x00010000;
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} else {
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if (memtype & 0x80000000)
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flags5 = 0x00000000; /* large pages */
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else
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flags5 = 0x00020000;
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}
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nv_wo32(disp->ramin, dmao + 0x00, 0x0019003d | (memtype << 22));
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nv_wo32(disp->ramin, dmao + 0x04, lower_32_bits(base + size - 1));
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nv_wo32(disp->ramin, dmao + 0x08, lower_32_bits(base));
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nv_wo32(disp->ramin, dmao + 0x0c, upper_32_bits(base + size - 1) << 24 |
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upper_32_bits(base));
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nv_wo32(disp->ramin, dmao + 0x10, 0x00000000);
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nv_wo32(disp->ramin, dmao + 0x14, flags5);
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nv_wo32(disp->ramin, hash + 0x00, handle);
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nv_wo32(disp->ramin, hash + 0x04, (evo->handle << 28) | (dmao << 10) |
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evo->handle);
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disp->dmao += 0x20;
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disp->hash += 0x08;
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return 0;
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}
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static int
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nv50_evo_channel_new(struct drm_device *dev, int chid,
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struct nouveau_channel **pevo)
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{
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struct nouveau_drm *drm = nouveau_drm(dev);
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struct nv50_display *disp = nv50_display(dev);
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struct nouveau_channel *evo;
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int ret;
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evo = kzalloc(sizeof(struct nouveau_channel), GFP_KERNEL);
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if (!evo)
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return -ENOMEM;
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*pevo = evo;
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evo->drm = drm;
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evo->handle = chid;
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evo->fence = dev;
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evo->user_get = 4;
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evo->user_put = 0;
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ret = nouveau_bo_new(dev, 4096, 0, TTM_PL_FLAG_VRAM, 0, 0, NULL,
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&evo->push.buffer);
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if (ret == 0)
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ret = nouveau_bo_pin(evo->push.buffer, TTM_PL_FLAG_VRAM);
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if (ret) {
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NV_ERROR(drm, "Error creating EVO DMA push buffer: %d\n", ret);
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nv50_evo_channel_del(pevo);
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return ret;
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}
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ret = nouveau_bo_map(evo->push.buffer);
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if (ret) {
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NV_ERROR(drm, "Error mapping EVO DMA push buffer: %d\n", ret);
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nv50_evo_channel_del(pevo);
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return ret;
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}
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evo->object = kzalloc(sizeof(*evo->object), GFP_KERNEL);
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#ifdef NOUVEAU_OBJECT_MAGIC
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evo->object->_magic = NOUVEAU_OBJECT_MAGIC;
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#endif
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evo->object->parent = nv_object(disp->ramin)->parent;
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evo->object->engine = nv_object(disp->ramin)->engine;
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evo->object->oclass =
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kzalloc(sizeof(*evo->object->oclass), GFP_KERNEL);
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evo->object->oclass->ofuncs =
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kzalloc(sizeof(*evo->object->oclass->ofuncs), GFP_KERNEL);
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evo->object->oclass->ofuncs->rd32 = nv50_evo_rd32;
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evo->object->oclass->ofuncs->wr32 = nv50_evo_wr32;
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evo->object->oclass->ofuncs->rd08 =
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ioremap(pci_resource_start(dev->pdev, 0) +
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NV50_PDISPLAY_USER(evo->handle), PAGE_SIZE);
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return 0;
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}
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static int
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nv50_evo_channel_init(struct nouveau_channel *evo)
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{
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struct nouveau_drm *drm = evo->drm;
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struct nouveau_device *device = nv_device(drm->device);
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int id = evo->handle, ret, i;
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u64 pushbuf = evo->push.buffer->bo.offset;
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u32 tmp;
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tmp = nv_rd32(device, NV50_PDISPLAY_EVO_CTRL(id));
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if ((tmp & 0x009f0000) == 0x00020000)
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nv_wr32(device, NV50_PDISPLAY_EVO_CTRL(id), tmp | 0x00800000);
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tmp = nv_rd32(device, NV50_PDISPLAY_EVO_CTRL(id));
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if ((tmp & 0x003f0000) == 0x00030000)
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nv_wr32(device, NV50_PDISPLAY_EVO_CTRL(id), tmp | 0x00600000);
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/* initialise fifo */
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nv_wr32(device, NV50_PDISPLAY_EVO_DMA_CB(id), pushbuf >> 8 |
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NV50_PDISPLAY_EVO_DMA_CB_LOCATION_VRAM |
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NV50_PDISPLAY_EVO_DMA_CB_VALID);
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nv_wr32(device, NV50_PDISPLAY_EVO_UNK2(id), 0x00010000);
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nv_wr32(device, NV50_PDISPLAY_EVO_HASH_TAG(id), id);
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nv_mask(device, NV50_PDISPLAY_EVO_CTRL(id), NV50_PDISPLAY_EVO_CTRL_DMA,
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NV50_PDISPLAY_EVO_CTRL_DMA_ENABLED);
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nv_wr32(device, NV50_PDISPLAY_USER_PUT(id), 0x00000000);
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nv_wr32(device, NV50_PDISPLAY_EVO_CTRL(id), 0x01000003 |
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NV50_PDISPLAY_EVO_CTRL_DMA_ENABLED);
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if (!nv_wait(device, NV50_PDISPLAY_EVO_CTRL(id), 0x80000000, 0x00000000)) {
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NV_ERROR(drm, "EvoCh %d init timeout: 0x%08x\n", id,
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nv_rd32(device, NV50_PDISPLAY_EVO_CTRL(id)));
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return -EBUSY;
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}
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/* enable error reporting on the channel */
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nv_mask(device, 0x610028, 0x00000000, 0x00010001 << id);
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evo->dma.max = (4096/4) - 2;
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evo->dma.max &= ~7;
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evo->dma.put = 0;
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evo->dma.cur = evo->dma.put;
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evo->dma.free = evo->dma.max - evo->dma.cur;
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ret = RING_SPACE(evo, NOUVEAU_DMA_SKIPS);
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if (ret)
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return ret;
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for (i = 0; i < NOUVEAU_DMA_SKIPS; i++)
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OUT_RING(evo, 0);
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return 0;
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}
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static void
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nv50_evo_channel_fini(struct nouveau_channel *evo)
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{
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struct nouveau_drm *drm = evo->drm;
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struct nouveau_device *device = nv_device(drm->device);
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int id = evo->handle;
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nv_mask(device, 0x610028, 0x00010001 << id, 0x00000000);
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nv_mask(device, NV50_PDISPLAY_EVO_CTRL(id), 0x00001010, 0x00001000);
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nv_wr32(device, NV50_PDISPLAY_INTR_0, (1 << id));
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nv_mask(device, NV50_PDISPLAY_EVO_CTRL(id), 0x00000003, 0x00000000);
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if (!nv_wait(device, NV50_PDISPLAY_EVO_CTRL(id), 0x001e0000, 0x00000000)) {
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NV_ERROR(drm, "EvoCh %d takedown timeout: 0x%08x\n", id,
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nv_rd32(device, NV50_PDISPLAY_EVO_CTRL(id)));
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}
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}
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void
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nv50_evo_destroy(struct drm_device *dev)
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{
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struct nv50_display *disp = nv50_display(dev);
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int i;
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for (i = 0; i < 2; i++) {
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if (disp->crtc[i].sem.bo) {
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nouveau_bo_unmap(disp->crtc[i].sem.bo);
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nouveau_bo_ref(NULL, &disp->crtc[i].sem.bo);
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}
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nv50_evo_channel_del(&disp->crtc[i].sync);
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}
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nv50_evo_channel_del(&disp->master);
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nouveau_gpuobj_ref(NULL, &disp->ramin);
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}
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int
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nv50_evo_create(struct drm_device *dev)
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{
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struct nouveau_drm *drm = nouveau_drm(dev);
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struct nouveau_fb *pfb = nouveau_fb(drm->device);
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struct nv50_display *disp = nv50_display(dev);
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struct nouveau_channel *evo;
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int ret, i, j;
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/* setup object management on it, any other evo channel will
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* use this also as there's no per-channel support on the
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* hardware
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*/
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ret = nouveau_gpuobj_new(drm->device, NULL, 32768, 65536,
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NVOBJ_FLAG_ZERO_ALLOC, &disp->ramin);
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if (ret) {
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NV_ERROR(drm, "Error allocating EVO channel memory: %d\n", ret);
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goto err;
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}
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disp->hash = 0x0000;
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disp->dmao = 0x1000;
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/* create primary evo channel, the one we use for modesetting
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* purporses
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*/
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ret = nv50_evo_channel_new(dev, 0, &disp->master);
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if (ret)
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return ret;
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evo = disp->master;
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ret = nv50_evo_dmaobj_new(disp->master, NvEvoSync, 0x0000,
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disp->ramin->addr + 0x2000, 0x1000, NULL);
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if (ret)
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goto err;
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/* create some default objects for the scanout memtypes we support */
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ret = nv50_evo_dmaobj_new(disp->master, NvEvoVRAM, 0x0000,
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0, pfb->ram.size, NULL);
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if (ret)
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goto err;
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ret = nv50_evo_dmaobj_new(disp->master, NvEvoVRAM_LP, 0x80000000,
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0, pfb->ram.size, NULL);
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if (ret)
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goto err;
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ret = nv50_evo_dmaobj_new(disp->master, NvEvoFB32, 0x80000000 |
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(nv_device(drm->device)->chipset < 0xc0 ? 0x7a : 0xfe),
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0, pfb->ram.size, NULL);
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if (ret)
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goto err;
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ret = nv50_evo_dmaobj_new(disp->master, NvEvoFB16, 0x80000000 |
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(nv_device(drm->device)->chipset < 0xc0 ? 0x70 : 0xfe),
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0, pfb->ram.size, NULL);
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if (ret)
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goto err;
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/* create "display sync" channels and other structures we need
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* to implement page flipping
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*/
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for (i = 0; i < 2; i++) {
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struct nv50_display_crtc *dispc = &disp->crtc[i];
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u64 offset;
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ret = nv50_evo_channel_new(dev, 1 + i, &dispc->sync);
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if (ret)
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goto err;
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ret = nouveau_bo_new(dev, 4096, 0x1000, TTM_PL_FLAG_VRAM,
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0, 0x0000, NULL, &dispc->sem.bo);
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if (!ret) {
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ret = nouveau_bo_pin(dispc->sem.bo, TTM_PL_FLAG_VRAM);
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if (!ret)
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ret = nouveau_bo_map(dispc->sem.bo);
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if (ret)
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nouveau_bo_ref(NULL, &dispc->sem.bo);
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offset = dispc->sem.bo->bo.offset;
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}
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if (ret)
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goto err;
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ret = nv50_evo_dmaobj_new(dispc->sync, NvEvoSync, 0x0000,
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offset, 4096, NULL);
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if (ret)
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goto err;
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ret = nv50_evo_dmaobj_new(dispc->sync, NvEvoVRAM_LP, 0x80000000,
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0, pfb->ram.size, NULL);
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if (ret)
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goto err;
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ret = nv50_evo_dmaobj_new(dispc->sync, NvEvoFB32, 0x80000000 |
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(nv_device(drm->device)->chipset < 0xc0 ?
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0x7a : 0xfe),
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0, pfb->ram.size, NULL);
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if (ret)
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goto err;
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ret = nv50_evo_dmaobj_new(dispc->sync, NvEvoFB16, 0x80000000 |
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(nv_device(drm->device)->chipset < 0xc0 ?
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0x70 : 0xfe),
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0, pfb->ram.size, NULL);
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if (ret)
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goto err;
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for (j = 0; j < 4096; j += 4)
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nouveau_bo_wr32(dispc->sem.bo, j / 4, 0x74b1e000);
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dispc->sem.offset = 0;
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}
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return 0;
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err:
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nv50_evo_destroy(dev);
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return ret;
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}
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int
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nv50_evo_init(struct drm_device *dev)
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{
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struct nv50_display *disp = nv50_display(dev);
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int ret, i;
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ret = nv50_evo_channel_init(disp->master);
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if (ret)
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return ret;
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for (i = 0; i < 2; i++) {
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ret = nv50_evo_channel_init(disp->crtc[i].sync);
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if (ret)
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return ret;
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}
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return 0;
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}
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void
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nv50_evo_fini(struct drm_device *dev)
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{
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struct nv50_display *disp = nv50_display(dev);
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int i;
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for (i = 0; i < 2; i++) {
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if (disp->crtc[i].sync)
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nv50_evo_channel_fini(disp->crtc[i].sync);
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}
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if (disp->master)
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nv50_evo_channel_fini(disp->master);
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}
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