Tony Cheng 6512387a54 drm/amd/display: align DCLK to voltage level ... in past program SMU will use all voltage headroom. RV does not if DAL need higher voltage for DCFCLK or DISPCLK, also increase FCLK to improve stutter as voltage is already Signed-off-by: Tony Cheng <tony.cheng@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2017-10-21 16:44:13 -04:00
..
drm	drm/amd/display: align DCLK to voltage level	2017-10-21 16:44:13 -04:00
host1x	drm/tegra: Changes for v4.14-rc1	2017-08-21 17:37:33 +10:00
ipu-v3	main drm pull request for 4.14 merge window	2017-09-03 17:02:26 -07:00
vga	sched/wait: Rename wait_queue_t => wait_queue_entry_t	2017-06-20 12:18:27 +02:00
Makefile