98e90a34cc
[Why] In DCN we want direct DAL to SMU calls, with as little as possible interference by pplib. The reason for each pp_smu interface mapping to 1 SMU message is so we can have the sequencing of different SMU message in dal and shared across different OS. This will also simplify debugging as DAL owns this interaction and there's no confusion about division of ownership. [How] Part 2: Separate set_min_deep_sleep_dcfclk message from the SMU messages that are sent as part of dm_pp_apply_clock_for_voltage_request. Directly notify min dcfclk to smu Signed-off-by: Fatemeh Darbehani <fatemeh.darbehani@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
149 lines
4.2 KiB
C
149 lines
4.2 KiB
C
/*
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* Copyright 2017 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#ifndef DM_PP_SMU_IF__H
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#define DM_PP_SMU_IF__H
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/*
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* interface to PPLIB/SMU to setup clocks and pstate requirements on SoC
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*/
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enum pp_smu_ver {
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/*
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* PP_SMU_INTERFACE_X should be interpreted as the interface defined
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* starting from X, where X is some family of ASICs. This is as
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* opposed to interfaces used only for X. There will be some degree
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* of interface sharing between families of ASIcs.
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*/
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PP_SMU_UNSUPPORTED,
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PP_SMU_VER_RV
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};
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struct pp_smu {
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enum pp_smu_ver ver;
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const void *pp;
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/*
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* interim extra handle for backwards compatibility
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* as some existing functionality not yet implemented
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* by ppsmu
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*/
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const void *dm;
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};
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struct pp_smu_wm_set_range {
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unsigned int wm_inst;
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uint32_t min_fill_clk_khz;
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uint32_t max_fill_clk_khz;
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uint32_t min_drain_clk_khz;
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uint32_t max_drain_clk_khz;
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};
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#define MAX_WATERMARK_SETS 4
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struct pp_smu_wm_range_sets {
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unsigned int num_reader_wm_sets;
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struct pp_smu_wm_set_range reader_wm_sets[MAX_WATERMARK_SETS];
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unsigned int num_writer_wm_sets;
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struct pp_smu_wm_set_range writer_wm_sets[MAX_WATERMARK_SETS];
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};
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struct pp_smu_display_requirement_rv {
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/* PPSMC_MSG_SetDisplayCount: count
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* 0 triggers S0i2 optimization
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*/
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unsigned int display_count;
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/* PPSMC_MSG_SetHardMinFclkByFreq: khz
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* FCLK will vary with DPM, but never below requested hard min
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*/
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unsigned int hard_min_fclk_khz;
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/* PPSMC_MSG_SetHardMinDcefclkByFreq: khz
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* fixed clock at requested freq, either from FCH bypass or DFS
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*/
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unsigned int hard_min_dcefclk_khz;
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/* PPSMC_MSG_SetMinDeepSleepDcefclk: mhz
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* when DF is in cstate, dcf clock is further divided down
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* to just above given frequency
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*/
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unsigned int min_deep_sleep_dcefclk_mhz;
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};
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struct pp_smu_funcs_rv {
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struct pp_smu pp_smu;
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/* PPSMC_MSG_SetDisplayCount
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* 0 triggers S0i2 optimization
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*/
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void (*set_display_count)(struct pp_smu *pp, int count);
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/* which SMU message? are reader and writer WM separate SMU msg? */
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void (*set_wm_ranges)(struct pp_smu *pp,
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struct pp_smu_wm_range_sets *ranges);
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/* PPSMC_MSG_SetHardMinDcfclkByFreq
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* fixed clock at requested freq, either from FCH bypass or DFS
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*/
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void (*set_hard_min_dcfclk_by_freq)(struct pp_smu *pp, int mhz);
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/* PPSMC_MSG_SetMinDeepSleepDcfclk
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* when DF is in cstate, dcf clock is further divided down
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* to just above given frequency
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*/
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void (*set_min_deep_sleep_dcfclk)(struct pp_smu *pp, int mhz);
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/* PPSMC_MSG_SetHardMinFclkByFreq
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* FCLK will vary with DPM, but never below requested hard min
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*/
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void (*set_hard_min_fclk_by_freq)(struct pp_smu *pp, int mhz);
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/* PPSMC_MSG_SetHardMinSocclkByFreq
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* Needed for DWB support
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*/
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void (*set_hard_min_socclk_by_freq)(struct pp_smu *pp, int mhz);
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/* PME w/a */
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void (*set_pme_wa_enable)(struct pp_smu *pp);
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/*
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* Legacy functions. Used for backwards comp. with existing
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* PPlib code.
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*/
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void (*set_display_requirement)(struct pp_smu *pp,
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struct pp_smu_display_requirement_rv *req);
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};
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struct pp_smu_funcs {
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struct pp_smu ctx;
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union {
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struct pp_smu_funcs_rv rv_funcs;
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};
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};
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#endif /* DM_PP_SMU_IF__H */
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