Chris Park 6421c49567 drm/amd/display: DCEFCLK DS on CLK init ... [Why] On HG APU + dGPU scenario with no display to dGPU, DS stays disabled due to no display present. This problem can be worked around by DAL calling DCEFCLK DS message to SMU on clk init. [How] Call DCEFCLK DS message to SMU on clk init. Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Wayne Lin <wayne.lin@amd.com> Signed-off-by: Chris Park <Chris.Park@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2022-01-18 17:43:36 -05:00
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amdgpu_dm	drm/amd/display: Disabled seamless boots on DP and renamed power_down_display_on_boot	2022-01-18 17:41:18 -05:00
dc	drm/amd/display: DCEFCLK DS on CLK init	2022-01-18 17:43:36 -05:00
dmub	drm/amd/display: adjust bit comparison to be more type safe	2022-01-18 17:41:18 -05:00
include	drm/amd/display: Enable DSC over eDP	2021-11-22 14:45:01 -05:00
modules	drm/amd/display: unhard code link to phy idx mapping in dc link and clean up	2022-01-07 17:21:20 -05:00
Kconfig	drm/amdgpu/display: fix dependencies for DRM_AMD_DC_SI	2021-10-05 10:55:41 -04:00
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TODO