72e0642fb4
Split the act of building the ACR blob from firmware files from the rest of the (chip-dependent) secure boot logic. ACR logic is moved into acr_rxxx.c files, where rxxx corresponds to the compatible release of the NVIDIA driver. At the moment r352 and r361 are supported since firmwares have been released for these versions. Some abstractions are added on top of r352 so r361 can easily be implemented on top of it by just overriding a few hooks. This split makes it possible and easy to reuse the same ACR version on different chips. It also hopefully makes the code much more readable as the different secure boot logics are separated. As more chips and firmware versions will be supported, this is a necessity to not get lost in code that is already quite complex. This is a big commit, but it essentially moves things around (and split the nvkm_secboot structure into two, nvkm_secboot and nvkm_acr). Code semantics should not be affected. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
140 lines
4.2 KiB
C
140 lines
4.2 KiB
C
/*
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* Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include "acr.h"
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#include "gm200.h"
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#ifdef CONFIG_ARCH_TEGRA
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#define TEGRA_MC_BASE 0x70019000
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#define MC_SECURITY_CARVEOUT2_CFG0 0xc58
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#define MC_SECURITY_CARVEOUT2_BOM_0 0xc5c
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#define MC_SECURITY_CARVEOUT2_BOM_HI_0 0xc60
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#define MC_SECURITY_CARVEOUT2_SIZE_128K 0xc64
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#define TEGRA_MC_SECURITY_CARVEOUT_CFG_LOCKED (1 << 1)
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/**
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* sb_tegra_read_wpr() - read the WPR registers on Tegra
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*
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* On dGPU, we can manage the WPR region ourselves, but on Tegra the WPR region
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* is reserved from system memory by the bootloader and irreversibly locked.
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* This function reads the address and size of the pre-configured WPR region.
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*/
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static int
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gm20b_tegra_read_wpr(struct gm200_secboot *gsb)
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{
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struct nvkm_secboot *sb = &gsb->base;
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void __iomem *mc;
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u32 cfg;
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mc = ioremap(TEGRA_MC_BASE, 0xd00);
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if (!mc) {
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nvkm_error(&sb->subdev, "Cannot map Tegra MC registers\n");
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return PTR_ERR(mc);
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}
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sb->wpr_addr = ioread32_native(mc + MC_SECURITY_CARVEOUT2_BOM_0) |
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((u64)ioread32_native(mc + MC_SECURITY_CARVEOUT2_BOM_HI_0) << 32);
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sb->wpr_size = ioread32_native(mc + MC_SECURITY_CARVEOUT2_SIZE_128K)
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<< 17;
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cfg = ioread32_native(mc + MC_SECURITY_CARVEOUT2_CFG0);
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iounmap(mc);
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/* Check that WPR settings are valid */
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if (sb->wpr_size == 0) {
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nvkm_error(&sb->subdev, "WPR region is empty\n");
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return -EINVAL;
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}
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if (!(cfg & TEGRA_MC_SECURITY_CARVEOUT_CFG_LOCKED)) {
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nvkm_error(&sb->subdev, "WPR region not locked\n");
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return -EINVAL;
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}
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return 0;
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}
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#else
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static int
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gm20b_tegra_read_wpr(struct gm200_secboot *gsb)
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{
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nvkm_error(&gsb->base.subdev, "Tegra support not compiled in\n");
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return -EINVAL;
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}
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#endif
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static int
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gm20b_secboot_oneinit(struct nvkm_secboot *sb)
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{
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struct gm200_secboot *gsb = gm200_secboot(sb);
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int ret;
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ret = gm20b_tegra_read_wpr(gsb);
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if (ret)
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return ret;
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return gm200_secboot_oneinit(sb);
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}
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static const struct nvkm_secboot_func
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gm20b_secboot = {
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.dtor = gm200_secboot_dtor,
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.oneinit = gm20b_secboot_oneinit,
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.fini = gm200_secboot_fini,
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.run_blob = gm200_secboot_run_blob,
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};
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int
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gm20b_secboot_new(struct nvkm_device *device, int index,
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struct nvkm_secboot **psb)
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{
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int ret;
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struct gm200_secboot *gsb;
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struct nvkm_acr *acr;
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acr = acr_r352_new(BIT(NVKM_SECBOOT_FALCON_FECS));
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if (IS_ERR(acr))
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return PTR_ERR(acr);
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gsb = kzalloc(sizeof(*gsb), GFP_KERNEL);
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if (!gsb) {
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psb = NULL;
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return -ENOMEM;
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}
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*psb = &gsb->base;
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ret = nvkm_secboot_ctor(&gm20b_secboot, acr, device, index, &gsb->base);
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if (ret)
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return ret;
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return 0;
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}
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MODULE_FIRMWARE("nvidia/gm20b/acr/bl.bin");
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MODULE_FIRMWARE("nvidia/gm20b/acr/ucode_load.bin");
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MODULE_FIRMWARE("nvidia/gm20b/gr/fecs_bl.bin");
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MODULE_FIRMWARE("nvidia/gm20b/gr/fecs_inst.bin");
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MODULE_FIRMWARE("nvidia/gm20b/gr/fecs_data.bin");
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MODULE_FIRMWARE("nvidia/gm20b/gr/fecs_sig.bin");
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MODULE_FIRMWARE("nvidia/gm20b/gr/gpccs_inst.bin");
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MODULE_FIRMWARE("nvidia/gm20b/gr/gpccs_data.bin");
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MODULE_FIRMWARE("nvidia/gm20b/gr/sw_ctx.bin");
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MODULE_FIRMWARE("nvidia/gm20b/gr/sw_nonctx.bin");
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MODULE_FIRMWARE("nvidia/gm20b/gr/sw_bundle_init.bin");
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MODULE_FIRMWARE("nvidia/gm20b/gr/sw_method_init.bin");
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