forked from Minki/linux
f3c91c1dea
Under KMS, restoring the cursor is handled upon modeswitch in order to
avoid enabling an undefined set of registers. At the moment, the cursor
is restored before the aperture and modes are fully setup causing some
invalid access during resume, such as:
PGTBL_ER: 0x00040000
Invalid GTT entry during Cursor Fetch
Fix this by only performing cursor register save/restore under UMS where
it is done in the correct sequence.
Reported-by: Arkadiusz Miskiewicz <arekm@maven.pl>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
887 lines
28 KiB
C
887 lines
28 KiB
C
/*
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*
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* Copyright 2008 (c) Intel Corporation
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* Jesse Barnes <jbarnes@virtuousgeek.org>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
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* IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
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* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include "drmP.h"
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#include "drm.h"
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#include "i915_drm.h"
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#include "intel_drv.h"
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static bool i915_pipe_enabled(struct drm_device *dev, enum pipe pipe)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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u32 dpll_reg;
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if (HAS_PCH_SPLIT(dev)) {
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dpll_reg = (pipe == PIPE_A) ? PCH_DPLL_A: PCH_DPLL_B;
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} else {
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dpll_reg = (pipe == PIPE_A) ? DPLL_A: DPLL_B;
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}
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return (I915_READ(dpll_reg) & DPLL_VCO_ENABLE);
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}
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static void i915_save_palette(struct drm_device *dev, enum pipe pipe)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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unsigned long reg = (pipe == PIPE_A ? PALETTE_A : PALETTE_B);
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u32 *array;
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int i;
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if (!i915_pipe_enabled(dev, pipe))
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return;
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if (HAS_PCH_SPLIT(dev))
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reg = (pipe == PIPE_A) ? LGC_PALETTE_A : LGC_PALETTE_B;
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if (pipe == PIPE_A)
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array = dev_priv->save_palette_a;
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else
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array = dev_priv->save_palette_b;
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for(i = 0; i < 256; i++)
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array[i] = I915_READ(reg + (i << 2));
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}
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static void i915_restore_palette(struct drm_device *dev, enum pipe pipe)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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unsigned long reg = (pipe == PIPE_A ? PALETTE_A : PALETTE_B);
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u32 *array;
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int i;
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if (!i915_pipe_enabled(dev, pipe))
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return;
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if (HAS_PCH_SPLIT(dev))
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reg = (pipe == PIPE_A) ? LGC_PALETTE_A : LGC_PALETTE_B;
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if (pipe == PIPE_A)
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array = dev_priv->save_palette_a;
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else
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array = dev_priv->save_palette_b;
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for(i = 0; i < 256; i++)
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I915_WRITE(reg + (i << 2), array[i]);
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}
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static u8 i915_read_indexed(struct drm_device *dev, u16 index_port, u16 data_port, u8 reg)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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I915_WRITE8(index_port, reg);
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return I915_READ8(data_port);
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}
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static u8 i915_read_ar(struct drm_device *dev, u16 st01, u8 reg, u16 palette_enable)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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I915_READ8(st01);
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I915_WRITE8(VGA_AR_INDEX, palette_enable | reg);
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return I915_READ8(VGA_AR_DATA_READ);
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}
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static void i915_write_ar(struct drm_device *dev, u16 st01, u8 reg, u8 val, u16 palette_enable)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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I915_READ8(st01);
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I915_WRITE8(VGA_AR_INDEX, palette_enable | reg);
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I915_WRITE8(VGA_AR_DATA_WRITE, val);
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}
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static void i915_write_indexed(struct drm_device *dev, u16 index_port, u16 data_port, u8 reg, u8 val)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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I915_WRITE8(index_port, reg);
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I915_WRITE8(data_port, val);
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}
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static void i915_save_vga(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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int i;
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u16 cr_index, cr_data, st01;
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/* VGA color palette registers */
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dev_priv->saveDACMASK = I915_READ8(VGA_DACMASK);
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/* MSR bits */
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dev_priv->saveMSR = I915_READ8(VGA_MSR_READ);
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if (dev_priv->saveMSR & VGA_MSR_CGA_MODE) {
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cr_index = VGA_CR_INDEX_CGA;
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cr_data = VGA_CR_DATA_CGA;
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st01 = VGA_ST01_CGA;
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} else {
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cr_index = VGA_CR_INDEX_MDA;
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cr_data = VGA_CR_DATA_MDA;
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st01 = VGA_ST01_MDA;
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}
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/* CRT controller regs */
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i915_write_indexed(dev, cr_index, cr_data, 0x11,
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i915_read_indexed(dev, cr_index, cr_data, 0x11) &
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(~0x80));
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for (i = 0; i <= 0x24; i++)
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dev_priv->saveCR[i] =
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i915_read_indexed(dev, cr_index, cr_data, i);
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/* Make sure we don't turn off CR group 0 writes */
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dev_priv->saveCR[0x11] &= ~0x80;
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/* Attribute controller registers */
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I915_READ8(st01);
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dev_priv->saveAR_INDEX = I915_READ8(VGA_AR_INDEX);
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for (i = 0; i <= 0x14; i++)
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dev_priv->saveAR[i] = i915_read_ar(dev, st01, i, 0);
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I915_READ8(st01);
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I915_WRITE8(VGA_AR_INDEX, dev_priv->saveAR_INDEX);
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I915_READ8(st01);
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/* Graphics controller registers */
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for (i = 0; i < 9; i++)
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dev_priv->saveGR[i] =
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i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, i);
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dev_priv->saveGR[0x10] =
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i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x10);
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dev_priv->saveGR[0x11] =
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i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x11);
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dev_priv->saveGR[0x18] =
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i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x18);
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/* Sequencer registers */
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for (i = 0; i < 8; i++)
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dev_priv->saveSR[i] =
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i915_read_indexed(dev, VGA_SR_INDEX, VGA_SR_DATA, i);
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}
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static void i915_restore_vga(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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int i;
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u16 cr_index, cr_data, st01;
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/* MSR bits */
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I915_WRITE8(VGA_MSR_WRITE, dev_priv->saveMSR);
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if (dev_priv->saveMSR & VGA_MSR_CGA_MODE) {
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cr_index = VGA_CR_INDEX_CGA;
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cr_data = VGA_CR_DATA_CGA;
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st01 = VGA_ST01_CGA;
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} else {
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cr_index = VGA_CR_INDEX_MDA;
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cr_data = VGA_CR_DATA_MDA;
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st01 = VGA_ST01_MDA;
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}
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/* Sequencer registers, don't write SR07 */
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for (i = 0; i < 7; i++)
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i915_write_indexed(dev, VGA_SR_INDEX, VGA_SR_DATA, i,
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dev_priv->saveSR[i]);
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/* CRT controller regs */
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/* Enable CR group 0 writes */
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i915_write_indexed(dev, cr_index, cr_data, 0x11, dev_priv->saveCR[0x11]);
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for (i = 0; i <= 0x24; i++)
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i915_write_indexed(dev, cr_index, cr_data, i, dev_priv->saveCR[i]);
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/* Graphics controller regs */
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for (i = 0; i < 9; i++)
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i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, i,
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dev_priv->saveGR[i]);
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i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x10,
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dev_priv->saveGR[0x10]);
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i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x11,
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dev_priv->saveGR[0x11]);
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i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x18,
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dev_priv->saveGR[0x18]);
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/* Attribute controller registers */
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I915_READ8(st01); /* switch back to index mode */
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for (i = 0; i <= 0x14; i++)
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i915_write_ar(dev, st01, i, dev_priv->saveAR[i], 0);
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I915_READ8(st01); /* switch back to index mode */
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I915_WRITE8(VGA_AR_INDEX, dev_priv->saveAR_INDEX | 0x20);
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I915_READ8(st01);
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/* VGA color palette registers */
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I915_WRITE8(VGA_DACMASK, dev_priv->saveDACMASK);
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}
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static void i915_save_modeset_reg(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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if (drm_core_check_feature(dev, DRIVER_MODESET))
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return;
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/* Cursor state */
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dev_priv->saveCURACNTR = I915_READ(CURACNTR);
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dev_priv->saveCURAPOS = I915_READ(CURAPOS);
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dev_priv->saveCURABASE = I915_READ(CURABASE);
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dev_priv->saveCURBCNTR = I915_READ(CURBCNTR);
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dev_priv->saveCURBPOS = I915_READ(CURBPOS);
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dev_priv->saveCURBBASE = I915_READ(CURBBASE);
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if (IS_GEN2(dev))
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dev_priv->saveCURSIZE = I915_READ(CURSIZE);
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if (HAS_PCH_SPLIT(dev)) {
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dev_priv->savePCH_DREF_CONTROL = I915_READ(PCH_DREF_CONTROL);
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dev_priv->saveDISP_ARB_CTL = I915_READ(DISP_ARB_CTL);
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}
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/* Pipe & plane A info */
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dev_priv->savePIPEACONF = I915_READ(PIPEACONF);
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dev_priv->savePIPEASRC = I915_READ(PIPEASRC);
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if (HAS_PCH_SPLIT(dev)) {
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dev_priv->saveFPA0 = I915_READ(PCH_FPA0);
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dev_priv->saveFPA1 = I915_READ(PCH_FPA1);
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dev_priv->saveDPLL_A = I915_READ(PCH_DPLL_A);
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} else {
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dev_priv->saveFPA0 = I915_READ(FPA0);
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dev_priv->saveFPA1 = I915_READ(FPA1);
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dev_priv->saveDPLL_A = I915_READ(DPLL_A);
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}
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if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))
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dev_priv->saveDPLL_A_MD = I915_READ(DPLL_A_MD);
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dev_priv->saveHTOTAL_A = I915_READ(HTOTAL_A);
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dev_priv->saveHBLANK_A = I915_READ(HBLANK_A);
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dev_priv->saveHSYNC_A = I915_READ(HSYNC_A);
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dev_priv->saveVTOTAL_A = I915_READ(VTOTAL_A);
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dev_priv->saveVBLANK_A = I915_READ(VBLANK_A);
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dev_priv->saveVSYNC_A = I915_READ(VSYNC_A);
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if (!HAS_PCH_SPLIT(dev))
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dev_priv->saveBCLRPAT_A = I915_READ(BCLRPAT_A);
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if (HAS_PCH_SPLIT(dev)) {
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dev_priv->savePIPEA_DATA_M1 = I915_READ(PIPEA_DATA_M1);
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dev_priv->savePIPEA_DATA_N1 = I915_READ(PIPEA_DATA_N1);
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dev_priv->savePIPEA_LINK_M1 = I915_READ(PIPEA_LINK_M1);
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dev_priv->savePIPEA_LINK_N1 = I915_READ(PIPEA_LINK_N1);
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dev_priv->saveFDI_TXA_CTL = I915_READ(FDI_TXA_CTL);
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dev_priv->saveFDI_RXA_CTL = I915_READ(FDI_RXA_CTL);
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dev_priv->savePFA_CTL_1 = I915_READ(PFA_CTL_1);
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dev_priv->savePFA_WIN_SZ = I915_READ(PFA_WIN_SZ);
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dev_priv->savePFA_WIN_POS = I915_READ(PFA_WIN_POS);
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dev_priv->saveTRANSACONF = I915_READ(TRANSACONF);
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dev_priv->saveTRANS_HTOTAL_A = I915_READ(TRANS_HTOTAL_A);
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dev_priv->saveTRANS_HBLANK_A = I915_READ(TRANS_HBLANK_A);
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dev_priv->saveTRANS_HSYNC_A = I915_READ(TRANS_HSYNC_A);
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dev_priv->saveTRANS_VTOTAL_A = I915_READ(TRANS_VTOTAL_A);
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dev_priv->saveTRANS_VBLANK_A = I915_READ(TRANS_VBLANK_A);
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dev_priv->saveTRANS_VSYNC_A = I915_READ(TRANS_VSYNC_A);
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}
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dev_priv->saveDSPACNTR = I915_READ(DSPACNTR);
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dev_priv->saveDSPASTRIDE = I915_READ(DSPASTRIDE);
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dev_priv->saveDSPASIZE = I915_READ(DSPASIZE);
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dev_priv->saveDSPAPOS = I915_READ(DSPAPOS);
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dev_priv->saveDSPAADDR = I915_READ(DSPAADDR);
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if (INTEL_INFO(dev)->gen >= 4) {
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dev_priv->saveDSPASURF = I915_READ(DSPASURF);
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dev_priv->saveDSPATILEOFF = I915_READ(DSPATILEOFF);
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}
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i915_save_palette(dev, PIPE_A);
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dev_priv->savePIPEASTAT = I915_READ(PIPEASTAT);
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/* Pipe & plane B info */
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dev_priv->savePIPEBCONF = I915_READ(PIPEBCONF);
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dev_priv->savePIPEBSRC = I915_READ(PIPEBSRC);
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if (HAS_PCH_SPLIT(dev)) {
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dev_priv->saveFPB0 = I915_READ(PCH_FPB0);
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dev_priv->saveFPB1 = I915_READ(PCH_FPB1);
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dev_priv->saveDPLL_B = I915_READ(PCH_DPLL_B);
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} else {
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dev_priv->saveFPB0 = I915_READ(FPB0);
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dev_priv->saveFPB1 = I915_READ(FPB1);
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dev_priv->saveDPLL_B = I915_READ(DPLL_B);
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}
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if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))
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dev_priv->saveDPLL_B_MD = I915_READ(DPLL_B_MD);
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dev_priv->saveHTOTAL_B = I915_READ(HTOTAL_B);
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dev_priv->saveHBLANK_B = I915_READ(HBLANK_B);
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dev_priv->saveHSYNC_B = I915_READ(HSYNC_B);
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dev_priv->saveVTOTAL_B = I915_READ(VTOTAL_B);
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dev_priv->saveVBLANK_B = I915_READ(VBLANK_B);
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dev_priv->saveVSYNC_B = I915_READ(VSYNC_B);
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if (!HAS_PCH_SPLIT(dev))
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dev_priv->saveBCLRPAT_B = I915_READ(BCLRPAT_B);
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if (HAS_PCH_SPLIT(dev)) {
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dev_priv->savePIPEB_DATA_M1 = I915_READ(PIPEB_DATA_M1);
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dev_priv->savePIPEB_DATA_N1 = I915_READ(PIPEB_DATA_N1);
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dev_priv->savePIPEB_LINK_M1 = I915_READ(PIPEB_LINK_M1);
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dev_priv->savePIPEB_LINK_N1 = I915_READ(PIPEB_LINK_N1);
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dev_priv->saveFDI_TXB_CTL = I915_READ(FDI_TXB_CTL);
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dev_priv->saveFDI_RXB_CTL = I915_READ(FDI_RXB_CTL);
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dev_priv->savePFB_CTL_1 = I915_READ(PFB_CTL_1);
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dev_priv->savePFB_WIN_SZ = I915_READ(PFB_WIN_SZ);
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dev_priv->savePFB_WIN_POS = I915_READ(PFB_WIN_POS);
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dev_priv->saveTRANSBCONF = I915_READ(TRANSBCONF);
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dev_priv->saveTRANS_HTOTAL_B = I915_READ(TRANS_HTOTAL_B);
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dev_priv->saveTRANS_HBLANK_B = I915_READ(TRANS_HBLANK_B);
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dev_priv->saveTRANS_HSYNC_B = I915_READ(TRANS_HSYNC_B);
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dev_priv->saveTRANS_VTOTAL_B = I915_READ(TRANS_VTOTAL_B);
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dev_priv->saveTRANS_VBLANK_B = I915_READ(TRANS_VBLANK_B);
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dev_priv->saveTRANS_VSYNC_B = I915_READ(TRANS_VSYNC_B);
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}
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dev_priv->saveDSPBCNTR = I915_READ(DSPBCNTR);
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dev_priv->saveDSPBSTRIDE = I915_READ(DSPBSTRIDE);
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dev_priv->saveDSPBSIZE = I915_READ(DSPBSIZE);
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dev_priv->saveDSPBPOS = I915_READ(DSPBPOS);
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dev_priv->saveDSPBADDR = I915_READ(DSPBADDR);
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if (INTEL_INFO(dev)->gen >= 4) {
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dev_priv->saveDSPBSURF = I915_READ(DSPBSURF);
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dev_priv->saveDSPBTILEOFF = I915_READ(DSPBTILEOFF);
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}
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i915_save_palette(dev, PIPE_B);
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dev_priv->savePIPEBSTAT = I915_READ(PIPEBSTAT);
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return;
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}
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static void i915_restore_modeset_reg(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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int dpll_a_reg, fpa0_reg, fpa1_reg;
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int dpll_b_reg, fpb0_reg, fpb1_reg;
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if (drm_core_check_feature(dev, DRIVER_MODESET))
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return;
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if (HAS_PCH_SPLIT(dev)) {
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dpll_a_reg = PCH_DPLL_A;
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dpll_b_reg = PCH_DPLL_B;
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fpa0_reg = PCH_FPA0;
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fpb0_reg = PCH_FPB0;
|
|
fpa1_reg = PCH_FPA1;
|
|
fpb1_reg = PCH_FPB1;
|
|
} else {
|
|
dpll_a_reg = DPLL_A;
|
|
dpll_b_reg = DPLL_B;
|
|
fpa0_reg = FPA0;
|
|
fpb0_reg = FPB0;
|
|
fpa1_reg = FPA1;
|
|
fpb1_reg = FPB1;
|
|
}
|
|
|
|
if (HAS_PCH_SPLIT(dev)) {
|
|
I915_WRITE(PCH_DREF_CONTROL, dev_priv->savePCH_DREF_CONTROL);
|
|
I915_WRITE(DISP_ARB_CTL, dev_priv->saveDISP_ARB_CTL);
|
|
}
|
|
|
|
/* Pipe & plane A info */
|
|
/* Prime the clock */
|
|
if (dev_priv->saveDPLL_A & DPLL_VCO_ENABLE) {
|
|
I915_WRITE(dpll_a_reg, dev_priv->saveDPLL_A &
|
|
~DPLL_VCO_ENABLE);
|
|
POSTING_READ(dpll_a_reg);
|
|
udelay(150);
|
|
}
|
|
I915_WRITE(fpa0_reg, dev_priv->saveFPA0);
|
|
I915_WRITE(fpa1_reg, dev_priv->saveFPA1);
|
|
/* Actually enable it */
|
|
I915_WRITE(dpll_a_reg, dev_priv->saveDPLL_A);
|
|
POSTING_READ(dpll_a_reg);
|
|
udelay(150);
|
|
if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
|
|
I915_WRITE(DPLL_A_MD, dev_priv->saveDPLL_A_MD);
|
|
POSTING_READ(DPLL_A_MD);
|
|
}
|
|
udelay(150);
|
|
|
|
/* Restore mode */
|
|
I915_WRITE(HTOTAL_A, dev_priv->saveHTOTAL_A);
|
|
I915_WRITE(HBLANK_A, dev_priv->saveHBLANK_A);
|
|
I915_WRITE(HSYNC_A, dev_priv->saveHSYNC_A);
|
|
I915_WRITE(VTOTAL_A, dev_priv->saveVTOTAL_A);
|
|
I915_WRITE(VBLANK_A, dev_priv->saveVBLANK_A);
|
|
I915_WRITE(VSYNC_A, dev_priv->saveVSYNC_A);
|
|
if (!HAS_PCH_SPLIT(dev))
|
|
I915_WRITE(BCLRPAT_A, dev_priv->saveBCLRPAT_A);
|
|
|
|
if (HAS_PCH_SPLIT(dev)) {
|
|
I915_WRITE(PIPEA_DATA_M1, dev_priv->savePIPEA_DATA_M1);
|
|
I915_WRITE(PIPEA_DATA_N1, dev_priv->savePIPEA_DATA_N1);
|
|
I915_WRITE(PIPEA_LINK_M1, dev_priv->savePIPEA_LINK_M1);
|
|
I915_WRITE(PIPEA_LINK_N1, dev_priv->savePIPEA_LINK_N1);
|
|
|
|
I915_WRITE(FDI_RXA_CTL, dev_priv->saveFDI_RXA_CTL);
|
|
I915_WRITE(FDI_TXA_CTL, dev_priv->saveFDI_TXA_CTL);
|
|
|
|
I915_WRITE(PFA_CTL_1, dev_priv->savePFA_CTL_1);
|
|
I915_WRITE(PFA_WIN_SZ, dev_priv->savePFA_WIN_SZ);
|
|
I915_WRITE(PFA_WIN_POS, dev_priv->savePFA_WIN_POS);
|
|
|
|
I915_WRITE(TRANSACONF, dev_priv->saveTRANSACONF);
|
|
I915_WRITE(TRANS_HTOTAL_A, dev_priv->saveTRANS_HTOTAL_A);
|
|
I915_WRITE(TRANS_HBLANK_A, dev_priv->saveTRANS_HBLANK_A);
|
|
I915_WRITE(TRANS_HSYNC_A, dev_priv->saveTRANS_HSYNC_A);
|
|
I915_WRITE(TRANS_VTOTAL_A, dev_priv->saveTRANS_VTOTAL_A);
|
|
I915_WRITE(TRANS_VBLANK_A, dev_priv->saveTRANS_VBLANK_A);
|
|
I915_WRITE(TRANS_VSYNC_A, dev_priv->saveTRANS_VSYNC_A);
|
|
}
|
|
|
|
/* Restore plane info */
|
|
I915_WRITE(DSPASIZE, dev_priv->saveDSPASIZE);
|
|
I915_WRITE(DSPAPOS, dev_priv->saveDSPAPOS);
|
|
I915_WRITE(PIPEASRC, dev_priv->savePIPEASRC);
|
|
I915_WRITE(DSPAADDR, dev_priv->saveDSPAADDR);
|
|
I915_WRITE(DSPASTRIDE, dev_priv->saveDSPASTRIDE);
|
|
if (INTEL_INFO(dev)->gen >= 4) {
|
|
I915_WRITE(DSPASURF, dev_priv->saveDSPASURF);
|
|
I915_WRITE(DSPATILEOFF, dev_priv->saveDSPATILEOFF);
|
|
}
|
|
|
|
I915_WRITE(PIPEACONF, dev_priv->savePIPEACONF);
|
|
|
|
i915_restore_palette(dev, PIPE_A);
|
|
/* Enable the plane */
|
|
I915_WRITE(DSPACNTR, dev_priv->saveDSPACNTR);
|
|
I915_WRITE(DSPAADDR, I915_READ(DSPAADDR));
|
|
|
|
/* Pipe & plane B info */
|
|
if (dev_priv->saveDPLL_B & DPLL_VCO_ENABLE) {
|
|
I915_WRITE(dpll_b_reg, dev_priv->saveDPLL_B &
|
|
~DPLL_VCO_ENABLE);
|
|
POSTING_READ(dpll_b_reg);
|
|
udelay(150);
|
|
}
|
|
I915_WRITE(fpb0_reg, dev_priv->saveFPB0);
|
|
I915_WRITE(fpb1_reg, dev_priv->saveFPB1);
|
|
/* Actually enable it */
|
|
I915_WRITE(dpll_b_reg, dev_priv->saveDPLL_B);
|
|
POSTING_READ(dpll_b_reg);
|
|
udelay(150);
|
|
if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
|
|
I915_WRITE(DPLL_B_MD, dev_priv->saveDPLL_B_MD);
|
|
POSTING_READ(DPLL_B_MD);
|
|
}
|
|
udelay(150);
|
|
|
|
/* Restore mode */
|
|
I915_WRITE(HTOTAL_B, dev_priv->saveHTOTAL_B);
|
|
I915_WRITE(HBLANK_B, dev_priv->saveHBLANK_B);
|
|
I915_WRITE(HSYNC_B, dev_priv->saveHSYNC_B);
|
|
I915_WRITE(VTOTAL_B, dev_priv->saveVTOTAL_B);
|
|
I915_WRITE(VBLANK_B, dev_priv->saveVBLANK_B);
|
|
I915_WRITE(VSYNC_B, dev_priv->saveVSYNC_B);
|
|
if (!HAS_PCH_SPLIT(dev))
|
|
I915_WRITE(BCLRPAT_B, dev_priv->saveBCLRPAT_B);
|
|
|
|
if (HAS_PCH_SPLIT(dev)) {
|
|
I915_WRITE(PIPEB_DATA_M1, dev_priv->savePIPEB_DATA_M1);
|
|
I915_WRITE(PIPEB_DATA_N1, dev_priv->savePIPEB_DATA_N1);
|
|
I915_WRITE(PIPEB_LINK_M1, dev_priv->savePIPEB_LINK_M1);
|
|
I915_WRITE(PIPEB_LINK_N1, dev_priv->savePIPEB_LINK_N1);
|
|
|
|
I915_WRITE(FDI_RXB_CTL, dev_priv->saveFDI_RXB_CTL);
|
|
I915_WRITE(FDI_TXB_CTL, dev_priv->saveFDI_TXB_CTL);
|
|
|
|
I915_WRITE(PFB_CTL_1, dev_priv->savePFB_CTL_1);
|
|
I915_WRITE(PFB_WIN_SZ, dev_priv->savePFB_WIN_SZ);
|
|
I915_WRITE(PFB_WIN_POS, dev_priv->savePFB_WIN_POS);
|
|
|
|
I915_WRITE(TRANSBCONF, dev_priv->saveTRANSBCONF);
|
|
I915_WRITE(TRANS_HTOTAL_B, dev_priv->saveTRANS_HTOTAL_B);
|
|
I915_WRITE(TRANS_HBLANK_B, dev_priv->saveTRANS_HBLANK_B);
|
|
I915_WRITE(TRANS_HSYNC_B, dev_priv->saveTRANS_HSYNC_B);
|
|
I915_WRITE(TRANS_VTOTAL_B, dev_priv->saveTRANS_VTOTAL_B);
|
|
I915_WRITE(TRANS_VBLANK_B, dev_priv->saveTRANS_VBLANK_B);
|
|
I915_WRITE(TRANS_VSYNC_B, dev_priv->saveTRANS_VSYNC_B);
|
|
}
|
|
|
|
/* Restore plane info */
|
|
I915_WRITE(DSPBSIZE, dev_priv->saveDSPBSIZE);
|
|
I915_WRITE(DSPBPOS, dev_priv->saveDSPBPOS);
|
|
I915_WRITE(PIPEBSRC, dev_priv->savePIPEBSRC);
|
|
I915_WRITE(DSPBADDR, dev_priv->saveDSPBADDR);
|
|
I915_WRITE(DSPBSTRIDE, dev_priv->saveDSPBSTRIDE);
|
|
if (INTEL_INFO(dev)->gen >= 4) {
|
|
I915_WRITE(DSPBSURF, dev_priv->saveDSPBSURF);
|
|
I915_WRITE(DSPBTILEOFF, dev_priv->saveDSPBTILEOFF);
|
|
}
|
|
|
|
I915_WRITE(PIPEBCONF, dev_priv->savePIPEBCONF);
|
|
|
|
i915_restore_palette(dev, PIPE_B);
|
|
/* Enable the plane */
|
|
I915_WRITE(DSPBCNTR, dev_priv->saveDSPBCNTR);
|
|
I915_WRITE(DSPBADDR, I915_READ(DSPBADDR));
|
|
|
|
/* Cursor state */
|
|
I915_WRITE(CURAPOS, dev_priv->saveCURAPOS);
|
|
I915_WRITE(CURACNTR, dev_priv->saveCURACNTR);
|
|
I915_WRITE(CURABASE, dev_priv->saveCURABASE);
|
|
I915_WRITE(CURBPOS, dev_priv->saveCURBPOS);
|
|
I915_WRITE(CURBCNTR, dev_priv->saveCURBCNTR);
|
|
I915_WRITE(CURBBASE, dev_priv->saveCURBBASE);
|
|
if (IS_GEN2(dev))
|
|
I915_WRITE(CURSIZE, dev_priv->saveCURSIZE);
|
|
|
|
return;
|
|
}
|
|
|
|
void i915_save_display(struct drm_device *dev)
|
|
{
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
/* Display arbitration control */
|
|
dev_priv->saveDSPARB = I915_READ(DSPARB);
|
|
|
|
/* This is only meaningful in non-KMS mode */
|
|
/* Don't save them in KMS mode */
|
|
i915_save_modeset_reg(dev);
|
|
|
|
/* CRT state */
|
|
if (HAS_PCH_SPLIT(dev)) {
|
|
dev_priv->saveADPA = I915_READ(PCH_ADPA);
|
|
} else {
|
|
dev_priv->saveADPA = I915_READ(ADPA);
|
|
}
|
|
|
|
/* LVDS state */
|
|
if (HAS_PCH_SPLIT(dev)) {
|
|
dev_priv->savePP_CONTROL = I915_READ(PCH_PP_CONTROL);
|
|
dev_priv->saveBLC_PWM_CTL = I915_READ(BLC_PWM_PCH_CTL1);
|
|
dev_priv->saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_PCH_CTL2);
|
|
dev_priv->saveBLC_CPU_PWM_CTL = I915_READ(BLC_PWM_CPU_CTL);
|
|
dev_priv->saveBLC_CPU_PWM_CTL2 = I915_READ(BLC_PWM_CPU_CTL2);
|
|
dev_priv->saveLVDS = I915_READ(PCH_LVDS);
|
|
} else {
|
|
dev_priv->savePP_CONTROL = I915_READ(PP_CONTROL);
|
|
dev_priv->savePFIT_PGM_RATIOS = I915_READ(PFIT_PGM_RATIOS);
|
|
dev_priv->saveBLC_PWM_CTL = I915_READ(BLC_PWM_CTL);
|
|
dev_priv->saveBLC_HIST_CTL = I915_READ(BLC_HIST_CTL);
|
|
if (INTEL_INFO(dev)->gen >= 4)
|
|
dev_priv->saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_CTL2);
|
|
if (IS_MOBILE(dev) && !IS_I830(dev))
|
|
dev_priv->saveLVDS = I915_READ(LVDS);
|
|
}
|
|
|
|
if (!IS_I830(dev) && !IS_845G(dev) && !HAS_PCH_SPLIT(dev))
|
|
dev_priv->savePFIT_CONTROL = I915_READ(PFIT_CONTROL);
|
|
|
|
if (HAS_PCH_SPLIT(dev)) {
|
|
dev_priv->savePP_ON_DELAYS = I915_READ(PCH_PP_ON_DELAYS);
|
|
dev_priv->savePP_OFF_DELAYS = I915_READ(PCH_PP_OFF_DELAYS);
|
|
dev_priv->savePP_DIVISOR = I915_READ(PCH_PP_DIVISOR);
|
|
} else {
|
|
dev_priv->savePP_ON_DELAYS = I915_READ(PP_ON_DELAYS);
|
|
dev_priv->savePP_OFF_DELAYS = I915_READ(PP_OFF_DELAYS);
|
|
dev_priv->savePP_DIVISOR = I915_READ(PP_DIVISOR);
|
|
}
|
|
|
|
/* Display Port state */
|
|
if (SUPPORTS_INTEGRATED_DP(dev)) {
|
|
dev_priv->saveDP_B = I915_READ(DP_B);
|
|
dev_priv->saveDP_C = I915_READ(DP_C);
|
|
dev_priv->saveDP_D = I915_READ(DP_D);
|
|
dev_priv->savePIPEA_GMCH_DATA_M = I915_READ(PIPEA_GMCH_DATA_M);
|
|
dev_priv->savePIPEB_GMCH_DATA_M = I915_READ(PIPEB_GMCH_DATA_M);
|
|
dev_priv->savePIPEA_GMCH_DATA_N = I915_READ(PIPEA_GMCH_DATA_N);
|
|
dev_priv->savePIPEB_GMCH_DATA_N = I915_READ(PIPEB_GMCH_DATA_N);
|
|
dev_priv->savePIPEA_DP_LINK_M = I915_READ(PIPEA_DP_LINK_M);
|
|
dev_priv->savePIPEB_DP_LINK_M = I915_READ(PIPEB_DP_LINK_M);
|
|
dev_priv->savePIPEA_DP_LINK_N = I915_READ(PIPEA_DP_LINK_N);
|
|
dev_priv->savePIPEB_DP_LINK_N = I915_READ(PIPEB_DP_LINK_N);
|
|
}
|
|
/* FIXME: save TV & SDVO state */
|
|
|
|
/* Only save FBC state on the platform that supports FBC */
|
|
if (I915_HAS_FBC(dev)) {
|
|
if (HAS_PCH_SPLIT(dev)) {
|
|
dev_priv->saveDPFC_CB_BASE = I915_READ(ILK_DPFC_CB_BASE);
|
|
} else if (IS_GM45(dev)) {
|
|
dev_priv->saveDPFC_CB_BASE = I915_READ(DPFC_CB_BASE);
|
|
} else {
|
|
dev_priv->saveFBC_CFB_BASE = I915_READ(FBC_CFB_BASE);
|
|
dev_priv->saveFBC_LL_BASE = I915_READ(FBC_LL_BASE);
|
|
dev_priv->saveFBC_CONTROL2 = I915_READ(FBC_CONTROL2);
|
|
dev_priv->saveFBC_CONTROL = I915_READ(FBC_CONTROL);
|
|
}
|
|
}
|
|
|
|
/* VGA state */
|
|
dev_priv->saveVGA0 = I915_READ(VGA0);
|
|
dev_priv->saveVGA1 = I915_READ(VGA1);
|
|
dev_priv->saveVGA_PD = I915_READ(VGA_PD);
|
|
if (HAS_PCH_SPLIT(dev))
|
|
dev_priv->saveVGACNTRL = I915_READ(CPU_VGACNTRL);
|
|
else
|
|
dev_priv->saveVGACNTRL = I915_READ(VGACNTRL);
|
|
|
|
i915_save_vga(dev);
|
|
}
|
|
|
|
void i915_restore_display(struct drm_device *dev)
|
|
{
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
/* Display arbitration */
|
|
I915_WRITE(DSPARB, dev_priv->saveDSPARB);
|
|
|
|
/* Display port ratios (must be done before clock is set) */
|
|
if (SUPPORTS_INTEGRATED_DP(dev)) {
|
|
I915_WRITE(PIPEA_GMCH_DATA_M, dev_priv->savePIPEA_GMCH_DATA_M);
|
|
I915_WRITE(PIPEB_GMCH_DATA_M, dev_priv->savePIPEB_GMCH_DATA_M);
|
|
I915_WRITE(PIPEA_GMCH_DATA_N, dev_priv->savePIPEA_GMCH_DATA_N);
|
|
I915_WRITE(PIPEB_GMCH_DATA_N, dev_priv->savePIPEB_GMCH_DATA_N);
|
|
I915_WRITE(PIPEA_DP_LINK_M, dev_priv->savePIPEA_DP_LINK_M);
|
|
I915_WRITE(PIPEB_DP_LINK_M, dev_priv->savePIPEB_DP_LINK_M);
|
|
I915_WRITE(PIPEA_DP_LINK_N, dev_priv->savePIPEA_DP_LINK_N);
|
|
I915_WRITE(PIPEB_DP_LINK_N, dev_priv->savePIPEB_DP_LINK_N);
|
|
}
|
|
|
|
/* This is only meaningful in non-KMS mode */
|
|
/* Don't restore them in KMS mode */
|
|
i915_restore_modeset_reg(dev);
|
|
|
|
/* CRT state */
|
|
if (HAS_PCH_SPLIT(dev))
|
|
I915_WRITE(PCH_ADPA, dev_priv->saveADPA);
|
|
else
|
|
I915_WRITE(ADPA, dev_priv->saveADPA);
|
|
|
|
/* LVDS state */
|
|
if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))
|
|
I915_WRITE(BLC_PWM_CTL2, dev_priv->saveBLC_PWM_CTL2);
|
|
|
|
if (HAS_PCH_SPLIT(dev)) {
|
|
I915_WRITE(PCH_LVDS, dev_priv->saveLVDS);
|
|
} else if (IS_MOBILE(dev) && !IS_I830(dev))
|
|
I915_WRITE(LVDS, dev_priv->saveLVDS);
|
|
|
|
if (!IS_I830(dev) && !IS_845G(dev) && !HAS_PCH_SPLIT(dev))
|
|
I915_WRITE(PFIT_CONTROL, dev_priv->savePFIT_CONTROL);
|
|
|
|
if (HAS_PCH_SPLIT(dev)) {
|
|
I915_WRITE(BLC_PWM_PCH_CTL1, dev_priv->saveBLC_PWM_CTL);
|
|
I915_WRITE(BLC_PWM_PCH_CTL2, dev_priv->saveBLC_PWM_CTL2);
|
|
I915_WRITE(BLC_PWM_CPU_CTL, dev_priv->saveBLC_CPU_PWM_CTL);
|
|
I915_WRITE(BLC_PWM_CPU_CTL2, dev_priv->saveBLC_CPU_PWM_CTL2);
|
|
I915_WRITE(PCH_PP_ON_DELAYS, dev_priv->savePP_ON_DELAYS);
|
|
I915_WRITE(PCH_PP_OFF_DELAYS, dev_priv->savePP_OFF_DELAYS);
|
|
I915_WRITE(PCH_PP_DIVISOR, dev_priv->savePP_DIVISOR);
|
|
I915_WRITE(PCH_PP_CONTROL, dev_priv->savePP_CONTROL);
|
|
I915_WRITE(MCHBAR_RENDER_STANDBY,
|
|
dev_priv->saveMCHBAR_RENDER_STANDBY);
|
|
} else {
|
|
I915_WRITE(PFIT_PGM_RATIOS, dev_priv->savePFIT_PGM_RATIOS);
|
|
I915_WRITE(BLC_PWM_CTL, dev_priv->saveBLC_PWM_CTL);
|
|
I915_WRITE(BLC_HIST_CTL, dev_priv->saveBLC_HIST_CTL);
|
|
I915_WRITE(PP_ON_DELAYS, dev_priv->savePP_ON_DELAYS);
|
|
I915_WRITE(PP_OFF_DELAYS, dev_priv->savePP_OFF_DELAYS);
|
|
I915_WRITE(PP_DIVISOR, dev_priv->savePP_DIVISOR);
|
|
I915_WRITE(PP_CONTROL, dev_priv->savePP_CONTROL);
|
|
}
|
|
|
|
/* Display Port state */
|
|
if (SUPPORTS_INTEGRATED_DP(dev)) {
|
|
I915_WRITE(DP_B, dev_priv->saveDP_B);
|
|
I915_WRITE(DP_C, dev_priv->saveDP_C);
|
|
I915_WRITE(DP_D, dev_priv->saveDP_D);
|
|
}
|
|
/* FIXME: restore TV & SDVO state */
|
|
|
|
/* only restore FBC info on the platform that supports FBC*/
|
|
if (I915_HAS_FBC(dev)) {
|
|
if (HAS_PCH_SPLIT(dev)) {
|
|
ironlake_disable_fbc(dev);
|
|
I915_WRITE(ILK_DPFC_CB_BASE, dev_priv->saveDPFC_CB_BASE);
|
|
} else if (IS_GM45(dev)) {
|
|
g4x_disable_fbc(dev);
|
|
I915_WRITE(DPFC_CB_BASE, dev_priv->saveDPFC_CB_BASE);
|
|
} else {
|
|
i8xx_disable_fbc(dev);
|
|
I915_WRITE(FBC_CFB_BASE, dev_priv->saveFBC_CFB_BASE);
|
|
I915_WRITE(FBC_LL_BASE, dev_priv->saveFBC_LL_BASE);
|
|
I915_WRITE(FBC_CONTROL2, dev_priv->saveFBC_CONTROL2);
|
|
I915_WRITE(FBC_CONTROL, dev_priv->saveFBC_CONTROL);
|
|
}
|
|
}
|
|
/* VGA state */
|
|
if (HAS_PCH_SPLIT(dev))
|
|
I915_WRITE(CPU_VGACNTRL, dev_priv->saveVGACNTRL);
|
|
else
|
|
I915_WRITE(VGACNTRL, dev_priv->saveVGACNTRL);
|
|
I915_WRITE(VGA0, dev_priv->saveVGA0);
|
|
I915_WRITE(VGA1, dev_priv->saveVGA1);
|
|
I915_WRITE(VGA_PD, dev_priv->saveVGA_PD);
|
|
POSTING_READ(VGA_PD);
|
|
udelay(150);
|
|
|
|
i915_restore_vga(dev);
|
|
}
|
|
|
|
int i915_save_state(struct drm_device *dev)
|
|
{
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
int i;
|
|
|
|
pci_read_config_byte(dev->pdev, LBB, &dev_priv->saveLBB);
|
|
|
|
/* Hardware status page */
|
|
dev_priv->saveHWS = I915_READ(HWS_PGA);
|
|
|
|
i915_save_display(dev);
|
|
|
|
/* Interrupt state */
|
|
if (HAS_PCH_SPLIT(dev)) {
|
|
dev_priv->saveDEIER = I915_READ(DEIER);
|
|
dev_priv->saveDEIMR = I915_READ(DEIMR);
|
|
dev_priv->saveGTIER = I915_READ(GTIER);
|
|
dev_priv->saveGTIMR = I915_READ(GTIMR);
|
|
dev_priv->saveFDI_RXA_IMR = I915_READ(FDI_RXA_IMR);
|
|
dev_priv->saveFDI_RXB_IMR = I915_READ(FDI_RXB_IMR);
|
|
dev_priv->saveMCHBAR_RENDER_STANDBY =
|
|
I915_READ(MCHBAR_RENDER_STANDBY);
|
|
} else {
|
|
dev_priv->saveIER = I915_READ(IER);
|
|
dev_priv->saveIMR = I915_READ(IMR);
|
|
}
|
|
|
|
if (HAS_PCH_SPLIT(dev))
|
|
ironlake_disable_drps(dev);
|
|
|
|
/* Cache mode state */
|
|
dev_priv->saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0);
|
|
|
|
/* Memory Arbitration state */
|
|
dev_priv->saveMI_ARB_STATE = I915_READ(MI_ARB_STATE);
|
|
|
|
/* Scratch space */
|
|
for (i = 0; i < 16; i++) {
|
|
dev_priv->saveSWF0[i] = I915_READ(SWF00 + (i << 2));
|
|
dev_priv->saveSWF1[i] = I915_READ(SWF10 + (i << 2));
|
|
}
|
|
for (i = 0; i < 3; i++)
|
|
dev_priv->saveSWF2[i] = I915_READ(SWF30 + (i << 2));
|
|
|
|
/* Fences */
|
|
switch (INTEL_INFO(dev)->gen) {
|
|
case 6:
|
|
for (i = 0; i < 16; i++)
|
|
dev_priv->saveFENCE[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
|
|
break;
|
|
case 5:
|
|
case 4:
|
|
for (i = 0; i < 16; i++)
|
|
dev_priv->saveFENCE[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
|
|
break;
|
|
case 3:
|
|
if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
|
|
for (i = 0; i < 8; i++)
|
|
dev_priv->saveFENCE[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
|
|
case 2:
|
|
for (i = 0; i < 8; i++)
|
|
dev_priv->saveFENCE[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
|
|
break;
|
|
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
int i915_restore_state(struct drm_device *dev)
|
|
{
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
int i;
|
|
|
|
pci_write_config_byte(dev->pdev, LBB, dev_priv->saveLBB);
|
|
|
|
/* Hardware status page */
|
|
I915_WRITE(HWS_PGA, dev_priv->saveHWS);
|
|
|
|
/* Fences */
|
|
switch (INTEL_INFO(dev)->gen) {
|
|
case 6:
|
|
for (i = 0; i < 16; i++)
|
|
I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (i * 8), dev_priv->saveFENCE[i]);
|
|
break;
|
|
case 5:
|
|
case 4:
|
|
for (i = 0; i < 16; i++)
|
|
I915_WRITE64(FENCE_REG_965_0 + (i * 8), dev_priv->saveFENCE[i]);
|
|
break;
|
|
case 3:
|
|
case 2:
|
|
if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
|
|
for (i = 0; i < 8; i++)
|
|
I915_WRITE(FENCE_REG_945_8 + (i * 4), dev_priv->saveFENCE[i+8]);
|
|
for (i = 0; i < 8; i++)
|
|
I915_WRITE(FENCE_REG_830_0 + (i * 4), dev_priv->saveFENCE[i]);
|
|
break;
|
|
}
|
|
|
|
i915_restore_display(dev);
|
|
|
|
/* Interrupt state */
|
|
if (HAS_PCH_SPLIT(dev)) {
|
|
I915_WRITE(DEIER, dev_priv->saveDEIER);
|
|
I915_WRITE(DEIMR, dev_priv->saveDEIMR);
|
|
I915_WRITE(GTIER, dev_priv->saveGTIER);
|
|
I915_WRITE(GTIMR, dev_priv->saveGTIMR);
|
|
I915_WRITE(FDI_RXA_IMR, dev_priv->saveFDI_RXA_IMR);
|
|
I915_WRITE(FDI_RXB_IMR, dev_priv->saveFDI_RXB_IMR);
|
|
} else {
|
|
I915_WRITE (IER, dev_priv->saveIER);
|
|
I915_WRITE (IMR, dev_priv->saveIMR);
|
|
}
|
|
|
|
/* Clock gating state */
|
|
intel_init_clock_gating(dev);
|
|
|
|
if (HAS_PCH_SPLIT(dev)) {
|
|
ironlake_enable_drps(dev);
|
|
intel_init_emon(dev);
|
|
}
|
|
|
|
/* Cache mode state */
|
|
I915_WRITE (CACHE_MODE_0, dev_priv->saveCACHE_MODE_0 | 0xffff0000);
|
|
|
|
/* Memory arbitration state */
|
|
I915_WRITE (MI_ARB_STATE, dev_priv->saveMI_ARB_STATE | 0xffff0000);
|
|
|
|
for (i = 0; i < 16; i++) {
|
|
I915_WRITE(SWF00 + (i << 2), dev_priv->saveSWF0[i]);
|
|
I915_WRITE(SWF10 + (i << 2), dev_priv->saveSWF1[i]);
|
|
}
|
|
for (i = 0; i < 3; i++)
|
|
I915_WRITE(SWF30 + (i << 2), dev_priv->saveSWF2[i]);
|
|
|
|
intel_i2c_reset(dev);
|
|
|
|
return 0;
|
|
}
|