forked from Minki/linux
5ead97c84f
This patch is a rollup of all the core pieces of the Xen
implementation, including:
- booting and setup
- pagetable setup
- privileged instructions
- segmentation
- interrupt flags
- upcalls
- multicall batching
BOOTING AND SETUP
The vmlinux image is decorated with ELF notes which tell the Xen
domain builder what the kernel's requirements are; the domain builder
then constructs the address space accordingly and starts the kernel.
Xen has its own entrypoint for the kernel (contained in an ELF note).
The ELF notes are set up by xen-head.S, which is included into head.S.
In principle it could be linked separately, but it seems to provoke
lots of binutils bugs.
Because the domain builder starts the kernel in a fairly sane state
(32-bit protected mode, paging enabled, flat segments set up), there's
not a lot of setup needed before starting the kernel proper. The main
steps are:
1. Install the Xen paravirt_ops, which is simply a matter of a
structure assignment.
2. Set init_mm to use the Xen-supplied pagetables (analogous to the
head.S generated pagetables in a native boot).
3. Reserve address space for Xen, since it takes a chunk at the top
of the address space for its own use.
4. Call start_kernel()
PAGETABLE SETUP
Once we hit the main kernel boot sequence, it will end up calling back
via paravirt_ops to set up various pieces of Xen specific state. One
of the critical things which requires a bit of extra care is the
construction of the initial init_mm pagetable. Because Xen places
tight constraints on pagetables (an active pagetable must always be
valid, and must always be mapped read-only to the guest domain), we
need to be careful when constructing the new pagetable to keep these
constraints in mind. It turns out that the easiest way to do this is
use the initial Xen-provided pagetable as a template, and then just
insert new mappings for memory where a mapping doesn't already exist.
This means that during pagetable setup, it uses a special version of
xen_set_pte which ignores any attempt to remap a read-only page as
read-write (since Xen will map its own initial pagetable as RO), but
lets other changes to the ptes happen, so that things like NX are set
properly.
PRIVILEGED INSTRUCTIONS AND SEGMENTATION
When the kernel runs under Xen, it runs in ring 1 rather than ring 0.
This means that it is more privileged than user-mode in ring 3, but it
still can't run privileged instructions directly. Non-performance
critical instructions are dealt with by taking a privilege exception
and trapping into the hypervisor and emulating the instruction, but
more performance-critical instructions have their own specific
paravirt_ops. In many cases we can avoid having to do any hypercalls
for these instructions, or the Xen implementation is quite different
from the normal native version.
The privileged instructions fall into the broad classes of:
Segmentation: setting up the GDT and the GDT entries, LDT,
TLS and so on. Xen doesn't allow the GDT to be directly
modified; all GDT updates are done via hypercalls where the new
entries can be validated. This is important because Xen uses
segment limits to prevent the guest kernel from damaging the
hypervisor itself.
Traps and exceptions: Xen uses a special format for trap entrypoints,
so when the kernel wants to set an IDT entry, it needs to be
converted to the form Xen expects. Xen sets int 0x80 up specially
so that the trap goes straight from userspace into the guest kernel
without going via the hypervisor. sysenter isn't supported.
Kernel stack: The esp0 entry is extracted from the tss and provided to
Xen.
TLB operations: the various TLB calls are mapped into corresponding
Xen hypercalls.
Control registers: all the control registers are privileged. The most
important is cr3, which points to the base of the current pagetable,
and we handle it specially.
Another instruction we treat specially is CPUID, even though its not
privileged. We want to control what CPU features are visible to the
rest of the kernel, and so CPUID ends up going into a paravirt_op.
Xen implements this mainly to disable the ACPI and APIC subsystems.
INTERRUPT FLAGS
Xen maintains its own separate flag for masking events, which is
contained within the per-cpu vcpu_info structure. Because the guest
kernel runs in ring 1 and not 0, the IF flag in EFLAGS is completely
ignored (and must be, because even if a guest domain disables
interrupts for itself, it can't disable them overall).
(A note on terminology: "events" and interrupts are effectively
synonymous. However, rather than using an "enable flag", Xen uses a
"mask flag", which blocks event delivery when it is non-zero.)
There are paravirt_ops for each of cli/sti/save_fl/restore_fl, which
are implemented to manage the Xen event mask state. The only thing
worth noting is that when events are unmasked, we need to explicitly
see if there's a pending event and call into the hypervisor to make
sure it gets delivered.
UPCALLS
Xen needs a couple of upcall (or callback) functions to be implemented
by each guest. One is the event upcalls, which is how events
(interrupts, effectively) are delivered to the guests. The other is
the failsafe callback, which is used to report errors in either
reloading a segment register, or caused by iret. These are
implemented in i386/kernel/entry.S so they can jump into the normal
iret_exc path when necessary.
MULTICALL BATCHING
Xen provides a multicall mechanism, which allows multiple hypercalls
to be issued at once in order to mitigate the cost of trapping into
the hypervisor. This is particularly useful for context switches,
since the 4-5 hypercalls they would normally need (reload cr3, update
TLS, maybe update LDT) can be reduced to one. This patch implements a
generic batching mechanism for hypercalls, which gets used in many
places in the Xen code.
Signed-off-by: Jeremy Fitzhardinge <jeremy@xensource.com>
Signed-off-by: Chris Wright <chrisw@sous-sol.org>
Cc: Ian Pratt <ian.pratt@xensource.com>
Cc: Christian Limpach <Christian.Limpach@cl.cam.ac.uk>
Cc: Adrian Bunk <bunk@stusta.de>
581 lines
14 KiB
ArmAsm
581 lines
14 KiB
ArmAsm
/*
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* linux/arch/i386/kernel/head.S -- the 32-bit startup code.
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*
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* Copyright (C) 1991, 1992 Linus Torvalds
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*
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* Enhanced CPU detection and feature setting code by Mike Jagdis
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* and Martin Mares, November 1997.
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*/
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.text
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#include <linux/threads.h>
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#include <linux/linkage.h>
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#include <asm/segment.h>
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#include <asm/page.h>
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#include <asm/pgtable.h>
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#include <asm/desc.h>
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#include <asm/cache.h>
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#include <asm/thread_info.h>
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#include <asm/asm-offsets.h>
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#include <asm/setup.h>
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/*
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* References to members of the new_cpu_data structure.
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*/
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#define X86 new_cpu_data+CPUINFO_x86
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#define X86_VENDOR new_cpu_data+CPUINFO_x86_vendor
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#define X86_MODEL new_cpu_data+CPUINFO_x86_model
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#define X86_MASK new_cpu_data+CPUINFO_x86_mask
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#define X86_HARD_MATH new_cpu_data+CPUINFO_hard_math
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#define X86_CPUID new_cpu_data+CPUINFO_cpuid_level
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#define X86_CAPABILITY new_cpu_data+CPUINFO_x86_capability
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#define X86_VENDOR_ID new_cpu_data+CPUINFO_x86_vendor_id
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/*
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* This is how much memory *in addition to the memory covered up to
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* and including _end* we need mapped initially.
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* We need:
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* - one bit for each possible page, but only in low memory, which means
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* 2^32/4096/8 = 128K worst case (4G/4G split.)
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* - enough space to map all low memory, which means
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* (2^32/4096) / 1024 pages (worst case, non PAE)
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* (2^32/4096) / 512 + 4 pages (worst case for PAE)
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* - a few pages for allocator use before the kernel pagetable has
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* been set up
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*
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* Modulo rounding, each megabyte assigned here requires a kilobyte of
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* memory, which is currently unreclaimed.
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*
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* This should be a multiple of a page.
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*/
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LOW_PAGES = 1<<(32-PAGE_SHIFT_asm)
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#if PTRS_PER_PMD > 1
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PAGE_TABLE_SIZE = (LOW_PAGES / PTRS_PER_PMD) + PTRS_PER_PGD
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#else
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PAGE_TABLE_SIZE = (LOW_PAGES / PTRS_PER_PGD)
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#endif
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BOOTBITMAP_SIZE = LOW_PAGES / 8
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ALLOCATOR_SLOP = 4
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INIT_MAP_BEYOND_END = BOOTBITMAP_SIZE + (PAGE_TABLE_SIZE + ALLOCATOR_SLOP)*PAGE_SIZE_asm
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/*
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* 32-bit kernel entrypoint; only used by the boot CPU. On entry,
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* %esi points to the real-mode code as a 32-bit pointer.
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* CS and DS must be 4 GB flat segments, but we don't depend on
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* any particular GDT layout, because we load our own as soon as we
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* can.
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*/
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.section .text.head,"ax",@progbits
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ENTRY(startup_32)
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/*
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* Set segments to known values.
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*/
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cld
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lgdt boot_gdt_descr - __PAGE_OFFSET
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movl $(__BOOT_DS),%eax
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movl %eax,%ds
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movl %eax,%es
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movl %eax,%fs
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movl %eax,%gs
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/*
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* Clear BSS first so that there are no surprises...
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* No need to cld as DF is already clear from cld above...
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*/
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xorl %eax,%eax
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movl $__bss_start - __PAGE_OFFSET,%edi
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movl $__bss_stop - __PAGE_OFFSET,%ecx
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subl %edi,%ecx
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shrl $2,%ecx
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rep ; stosl
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/*
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* Copy bootup parameters out of the way.
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* Note: %esi still has the pointer to the real-mode data.
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* With the kexec as boot loader, parameter segment might be loaded beyond
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* kernel image and might not even be addressable by early boot page tables.
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* (kexec on panic case). Hence copy out the parameters before initializing
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* page tables.
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*/
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movl $(boot_params - __PAGE_OFFSET),%edi
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movl $(PARAM_SIZE/4),%ecx
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cld
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rep
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movsl
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movl boot_params - __PAGE_OFFSET + NEW_CL_POINTER,%esi
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andl %esi,%esi
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jnz 2f # New command line protocol
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cmpw $(OLD_CL_MAGIC),OLD_CL_MAGIC_ADDR
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jne 1f
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movzwl OLD_CL_OFFSET,%esi
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addl $(OLD_CL_BASE_ADDR),%esi
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2:
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movl $(boot_command_line - __PAGE_OFFSET),%edi
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movl $(COMMAND_LINE_SIZE/4),%ecx
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rep
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movsl
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1:
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/*
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* Initialize page tables. This creates a PDE and a set of page
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* tables, which are located immediately beyond _end. The variable
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* init_pg_tables_end is set up to point to the first "safe" location.
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* Mappings are created both at virtual address 0 (identity mapping)
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* and PAGE_OFFSET for up to _end+sizeof(page tables)+INIT_MAP_BEYOND_END.
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*
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* Warning: don't use %esi or the stack in this code. However, %esp
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* can be used as a GPR if you really need it...
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*/
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page_pde_offset = (__PAGE_OFFSET >> 20);
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movl $(pg0 - __PAGE_OFFSET), %edi
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movl $(swapper_pg_dir - __PAGE_OFFSET), %edx
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movl $0x007, %eax /* 0x007 = PRESENT+RW+USER */
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10:
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leal 0x007(%edi),%ecx /* Create PDE entry */
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movl %ecx,(%edx) /* Store identity PDE entry */
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movl %ecx,page_pde_offset(%edx) /* Store kernel PDE entry */
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addl $4,%edx
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movl $1024, %ecx
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11:
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stosl
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addl $0x1000,%eax
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loop 11b
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/* End condition: we must map up to and including INIT_MAP_BEYOND_END */
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/* bytes beyond the end of our own page tables; the +0x007 is the attribute bits */
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leal (INIT_MAP_BEYOND_END+0x007)(%edi),%ebp
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cmpl %ebp,%eax
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jb 10b
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movl %edi,(init_pg_tables_end - __PAGE_OFFSET)
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xorl %ebx,%ebx /* This is the boot CPU (BSP) */
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jmp 3f
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/*
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* Non-boot CPU entry point; entered from trampoline.S
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* We can't lgdt here, because lgdt itself uses a data segment, but
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* we know the trampoline has already loaded the boot_gdt for us.
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*
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* If cpu hotplug is not supported then this code can go in init section
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* which will be freed later
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*/
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#ifdef CONFIG_HOTPLUG_CPU
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.section .text,"ax",@progbits
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#else
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.section .init.text,"ax",@progbits
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#endif
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/* Do an early initialization of the fixmap area */
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movl $(swapper_pg_dir - __PAGE_OFFSET), %edx
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movl $(swapper_pg_pmd - __PAGE_OFFSET), %eax
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addl $0x007, %eax /* 0x007 = PRESENT+RW+USER */
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movl %eax, 4092(%edx)
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#ifdef CONFIG_SMP
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ENTRY(startup_32_smp)
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cld
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movl $(__BOOT_DS),%eax
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movl %eax,%ds
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movl %eax,%es
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movl %eax,%fs
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movl %eax,%gs
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/*
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* New page tables may be in 4Mbyte page mode and may
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* be using the global pages.
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*
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* NOTE! If we are on a 486 we may have no cr4 at all!
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* So we do not try to touch it unless we really have
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* some bits in it to set. This won't work if the BSP
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* implements cr4 but this AP does not -- very unlikely
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* but be warned! The same applies to the pse feature
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* if not equally supported. --macro
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*
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* NOTE! We have to correct for the fact that we're
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* not yet offset PAGE_OFFSET..
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*/
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#define cr4_bits mmu_cr4_features-__PAGE_OFFSET
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movl cr4_bits,%edx
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andl %edx,%edx
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jz 6f
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movl %cr4,%eax # Turn on paging options (PSE,PAE,..)
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orl %edx,%eax
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movl %eax,%cr4
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btl $5, %eax # check if PAE is enabled
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jnc 6f
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/* Check if extended functions are implemented */
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movl $0x80000000, %eax
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cpuid
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cmpl $0x80000000, %eax
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jbe 6f
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mov $0x80000001, %eax
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cpuid
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/* Execute Disable bit supported? */
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btl $20, %edx
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jnc 6f
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/* Setup EFER (Extended Feature Enable Register) */
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movl $0xc0000080, %ecx
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rdmsr
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btsl $11, %eax
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/* Make changes effective */
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wrmsr
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6:
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/* This is a secondary processor (AP) */
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xorl %ebx,%ebx
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incl %ebx
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#endif /* CONFIG_SMP */
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3:
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/*
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* Enable paging
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*/
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movl $swapper_pg_dir-__PAGE_OFFSET,%eax
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movl %eax,%cr3 /* set the page table pointer.. */
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movl %cr0,%eax
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orl $0x80000000,%eax
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movl %eax,%cr0 /* ..and set paging (PG) bit */
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ljmp $__BOOT_CS,$1f /* Clear prefetch and normalize %eip */
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1:
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/* Set up the stack pointer */
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lss stack_start,%esp
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/*
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* Initialize eflags. Some BIOS's leave bits like NT set. This would
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* confuse the debugger if this code is traced.
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* XXX - best to initialize before switching to protected mode.
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*/
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pushl $0
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popfl
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#ifdef CONFIG_SMP
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andl %ebx,%ebx
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jz 1f /* Initial CPU cleans BSS */
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jmp checkCPUtype
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1:
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#endif /* CONFIG_SMP */
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/*
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* start system 32-bit setup. We need to re-do some of the things done
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* in 16-bit mode for the "real" operations.
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*/
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call setup_idt
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checkCPUtype:
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movl $-1,X86_CPUID # -1 for no CPUID initially
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/* check if it is 486 or 386. */
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/*
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* XXX - this does a lot of unnecessary setup. Alignment checks don't
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* apply at our cpl of 0 and the stack ought to be aligned already, and
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* we don't need to preserve eflags.
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*/
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movb $3,X86 # at least 386
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pushfl # push EFLAGS
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popl %eax # get EFLAGS
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movl %eax,%ecx # save original EFLAGS
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xorl $0x240000,%eax # flip AC and ID bits in EFLAGS
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pushl %eax # copy to EFLAGS
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popfl # set EFLAGS
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pushfl # get new EFLAGS
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popl %eax # put it in eax
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xorl %ecx,%eax # change in flags
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pushl %ecx # restore original EFLAGS
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popfl
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testl $0x40000,%eax # check if AC bit changed
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je is386
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movb $4,X86 # at least 486
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testl $0x200000,%eax # check if ID bit changed
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je is486
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/* get vendor info */
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xorl %eax,%eax # call CPUID with 0 -> return vendor ID
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cpuid
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movl %eax,X86_CPUID # save CPUID level
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movl %ebx,X86_VENDOR_ID # lo 4 chars
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movl %edx,X86_VENDOR_ID+4 # next 4 chars
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movl %ecx,X86_VENDOR_ID+8 # last 4 chars
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orl %eax,%eax # do we have processor info as well?
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je is486
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movl $1,%eax # Use the CPUID instruction to get CPU type
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cpuid
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movb %al,%cl # save reg for future use
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andb $0x0f,%ah # mask processor family
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movb %ah,X86
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andb $0xf0,%al # mask model
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shrb $4,%al
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movb %al,X86_MODEL
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andb $0x0f,%cl # mask mask revision
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movb %cl,X86_MASK
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movl %edx,X86_CAPABILITY
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is486: movl $0x50022,%ecx # set AM, WP, NE and MP
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jmp 2f
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is386: movl $2,%ecx # set MP
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2: movl %cr0,%eax
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andl $0x80000011,%eax # Save PG,PE,ET
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orl %ecx,%eax
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movl %eax,%cr0
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call check_x87
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lgdt early_gdt_descr
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lidt idt_descr
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ljmp $(__KERNEL_CS),$1f
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1: movl $(__KERNEL_DS),%eax # reload all the segment registers
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movl %eax,%ss # after changing gdt.
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movl %eax,%fs # gets reset once there's real percpu
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movl $(__USER_DS),%eax # DS/ES contains default USER segment
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movl %eax,%ds
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movl %eax,%es
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xorl %eax,%eax # Clear GS and LDT
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movl %eax,%gs
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lldt %ax
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cld # gcc2 wants the direction flag cleared at all times
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pushl $0 # fake return address for unwinder
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#ifdef CONFIG_SMP
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movb ready, %cl
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movb $1, ready
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cmpb $0,%cl # the first CPU calls start_kernel
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je 1f
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movl $(__KERNEL_PERCPU), %eax
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movl %eax,%fs # set this cpu's percpu
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jmp initialize_secondary # all other CPUs call initialize_secondary
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1:
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#endif /* CONFIG_SMP */
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jmp start_kernel
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/*
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* We depend on ET to be correct. This checks for 287/387.
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*/
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check_x87:
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movb $0,X86_HARD_MATH
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clts
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fninit
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fstsw %ax
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cmpb $0,%al
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je 1f
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movl %cr0,%eax /* no coprocessor: have to set bits */
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xorl $4,%eax /* set EM */
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movl %eax,%cr0
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ret
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ALIGN
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1: movb $1,X86_HARD_MATH
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.byte 0xDB,0xE4 /* fsetpm for 287, ignored by 387 */
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ret
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/*
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* setup_idt
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*
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* sets up a idt with 256 entries pointing to
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* ignore_int, interrupt gates. It doesn't actually load
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* idt - that can be done only after paging has been enabled
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* and the kernel moved to PAGE_OFFSET. Interrupts
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* are enabled elsewhere, when we can be relatively
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* sure everything is ok.
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*
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* Warning: %esi is live across this function.
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*/
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setup_idt:
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lea ignore_int,%edx
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movl $(__KERNEL_CS << 16),%eax
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movw %dx,%ax /* selector = 0x0010 = cs */
|
|
movw $0x8E00,%dx /* interrupt gate - dpl=0, present */
|
|
|
|
lea idt_table,%edi
|
|
mov $256,%ecx
|
|
rp_sidt:
|
|
movl %eax,(%edi)
|
|
movl %edx,4(%edi)
|
|
addl $8,%edi
|
|
dec %ecx
|
|
jne rp_sidt
|
|
|
|
.macro set_early_handler handler,trapno
|
|
lea \handler,%edx
|
|
movl $(__KERNEL_CS << 16),%eax
|
|
movw %dx,%ax
|
|
movw $0x8E00,%dx /* interrupt gate - dpl=0, present */
|
|
lea idt_table,%edi
|
|
movl %eax,8*\trapno(%edi)
|
|
movl %edx,8*\trapno+4(%edi)
|
|
.endm
|
|
|
|
set_early_handler handler=early_divide_err,trapno=0
|
|
set_early_handler handler=early_illegal_opcode,trapno=6
|
|
set_early_handler handler=early_protection_fault,trapno=13
|
|
set_early_handler handler=early_page_fault,trapno=14
|
|
|
|
ret
|
|
|
|
early_divide_err:
|
|
xor %edx,%edx
|
|
pushl $0 /* fake errcode */
|
|
jmp early_fault
|
|
|
|
early_illegal_opcode:
|
|
movl $6,%edx
|
|
pushl $0 /* fake errcode */
|
|
jmp early_fault
|
|
|
|
early_protection_fault:
|
|
movl $13,%edx
|
|
jmp early_fault
|
|
|
|
early_page_fault:
|
|
movl $14,%edx
|
|
jmp early_fault
|
|
|
|
early_fault:
|
|
cld
|
|
#ifdef CONFIG_PRINTK
|
|
movl $(__KERNEL_DS),%eax
|
|
movl %eax,%ds
|
|
movl %eax,%es
|
|
cmpl $2,early_recursion_flag
|
|
je hlt_loop
|
|
incl early_recursion_flag
|
|
movl %cr2,%eax
|
|
pushl %eax
|
|
pushl %edx /* trapno */
|
|
pushl $fault_msg
|
|
#ifdef CONFIG_EARLY_PRINTK
|
|
call early_printk
|
|
#else
|
|
call printk
|
|
#endif
|
|
#endif
|
|
hlt_loop:
|
|
hlt
|
|
jmp hlt_loop
|
|
|
|
/* This is the default interrupt "handler" :-) */
|
|
ALIGN
|
|
ignore_int:
|
|
cld
|
|
#ifdef CONFIG_PRINTK
|
|
pushl %eax
|
|
pushl %ecx
|
|
pushl %edx
|
|
pushl %es
|
|
pushl %ds
|
|
movl $(__KERNEL_DS),%eax
|
|
movl %eax,%ds
|
|
movl %eax,%es
|
|
cmpl $2,early_recursion_flag
|
|
je hlt_loop
|
|
incl early_recursion_flag
|
|
pushl 16(%esp)
|
|
pushl 24(%esp)
|
|
pushl 32(%esp)
|
|
pushl 40(%esp)
|
|
pushl $int_msg
|
|
#ifdef CONFIG_EARLY_PRINTK
|
|
call early_printk
|
|
#else
|
|
call printk
|
|
#endif
|
|
addl $(5*4),%esp
|
|
popl %ds
|
|
popl %es
|
|
popl %edx
|
|
popl %ecx
|
|
popl %eax
|
|
#endif
|
|
iret
|
|
|
|
.section .text
|
|
/*
|
|
* Real beginning of normal "text" segment
|
|
*/
|
|
ENTRY(stext)
|
|
ENTRY(_stext)
|
|
|
|
/*
|
|
* BSS section
|
|
*/
|
|
.section ".bss.page_aligned","wa"
|
|
.align PAGE_SIZE_asm
|
|
ENTRY(swapper_pg_dir)
|
|
.fill 1024,4,0
|
|
ENTRY(swapper_pg_pmd)
|
|
.fill 1024,4,0
|
|
ENTRY(empty_zero_page)
|
|
.fill 4096,1,0
|
|
|
|
/*
|
|
* This starts the data section.
|
|
*/
|
|
.data
|
|
ENTRY(stack_start)
|
|
.long init_thread_union+THREAD_SIZE
|
|
.long __BOOT_DS
|
|
|
|
ready: .byte 0
|
|
|
|
early_recursion_flag:
|
|
.long 0
|
|
|
|
int_msg:
|
|
.asciz "Unknown interrupt or fault at EIP %p %p %p\n"
|
|
|
|
fault_msg:
|
|
.ascii "Int %d: CR2 %p err %p EIP %p CS %p flags %p\n"
|
|
.asciz "Stack: %p %p %p %p %p %p %p %p\n"
|
|
|
|
#include "../xen/xen-head.S"
|
|
|
|
/*
|
|
* The IDT and GDT 'descriptors' are a strange 48-bit object
|
|
* only used by the lidt and lgdt instructions. They are not
|
|
* like usual segment descriptors - they consist of a 16-bit
|
|
* segment size, and 32-bit linear address value:
|
|
*/
|
|
|
|
.globl boot_gdt_descr
|
|
.globl idt_descr
|
|
|
|
ALIGN
|
|
# early boot GDT descriptor (must use 1:1 address mapping)
|
|
.word 0 # 32 bit align gdt_desc.address
|
|
boot_gdt_descr:
|
|
.word __BOOT_DS+7
|
|
.long boot_gdt - __PAGE_OFFSET
|
|
|
|
.word 0 # 32-bit align idt_desc.address
|
|
idt_descr:
|
|
.word IDT_ENTRIES*8-1 # idt contains 256 entries
|
|
.long idt_table
|
|
|
|
# boot GDT descriptor (later on used by CPU#0):
|
|
.word 0 # 32 bit align gdt_desc.address
|
|
ENTRY(early_gdt_descr)
|
|
.word GDT_ENTRIES*8-1
|
|
.long per_cpu__gdt_page /* Overwritten for secondary CPUs */
|
|
|
|
/*
|
|
* The boot_gdt must mirror the equivalent in setup.S and is
|
|
* used only for booting.
|
|
*/
|
|
.align L1_CACHE_BYTES
|
|
ENTRY(boot_gdt)
|
|
.fill GDT_ENTRY_BOOT_CS,8,0
|
|
.quad 0x00cf9a000000ffff /* kernel 4GB code at 0x00000000 */
|
|
.quad 0x00cf92000000ffff /* kernel 4GB data at 0x00000000 */
|