forked from Minki/linux
65fddcfca8
The replacement of <asm/pgrable.h> with <linux/pgtable.h> made the include
of the latter in the middle of asm includes. Fix this up with the aid of
the below script and manual adjustments here and there.
import sys
import re
if len(sys.argv) is not 3:
print "USAGE: %s <file> <header>" % (sys.argv[0])
sys.exit(1)
hdr_to_move="#include <linux/%s>" % sys.argv[2]
moved = False
in_hdrs = False
with open(sys.argv[1], "r") as f:
lines = f.readlines()
for _line in lines:
line = _line.rstrip('
')
if line == hdr_to_move:
continue
if line.startswith("#include <linux/"):
in_hdrs = True
elif not moved and in_hdrs:
moved = True
print hdr_to_move
print line
Signed-off-by: Mike Rapoport <rppt@linux.ibm.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Brian Cain <bcain@codeaurora.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Chris Zankel <chris@zankel.net>
Cc: "David S. Miller" <davem@davemloft.net>
Cc: Geert Uytterhoeven <geert@linux-m68k.org>
Cc: Greentime Hu <green.hu@gmail.com>
Cc: Greg Ungerer <gerg@linux-m68k.org>
Cc: Guan Xuetao <gxt@pku.edu.cn>
Cc: Guo Ren <guoren@kernel.org>
Cc: Heiko Carstens <heiko.carstens@de.ibm.com>
Cc: Helge Deller <deller@gmx.de>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
Cc: Mark Salter <msalter@redhat.com>
Cc: Matthew Wilcox <willy@infradead.org>
Cc: Matt Turner <mattst88@gmail.com>
Cc: Max Filippov <jcmvbkbc@gmail.com>
Cc: Michael Ellerman <mpe@ellerman.id.au>
Cc: Michal Simek <monstr@monstr.eu>
Cc: Nick Hu <nickhu@andestech.com>
Cc: Paul Walmsley <paul.walmsley@sifive.com>
Cc: Richard Weinberger <richard@nod.at>
Cc: Rich Felker <dalias@libc.org>
Cc: Russell King <linux@armlinux.org.uk>
Cc: Stafford Horne <shorne@gmail.com>
Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Tony Luck <tony.luck@intel.com>
Cc: Vincent Chen <deanbo422@gmail.com>
Cc: Vineet Gupta <vgupta@synopsys.com>
Cc: Will Deacon <will@kernel.org>
Cc: Yoshinori Sato <ysato@users.sourceforge.jp>
Link: http://lkml.kernel.org/r/20200514170327.31389-4-rppt@kernel.org
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
132 lines
2.5 KiB
ArmAsm
132 lines
2.5 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* linux/arch/unicore32/mm/proc-ucv2.S
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*
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* Code specific to PKUnity SoC and UniCore ISA
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*
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* Copyright (C) 2001-2010 GUAN Xue-tao
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*/
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#include <linux/init.h>
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#include <linux/linkage.h>
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#include <linux/pgtable.h>
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#include <asm/assembler.h>
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#include <asm/hwcap.h>
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#include <asm/pgtable-hwdef.h>
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#include "proc-macros.S"
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ENTRY(cpu_proc_fin)
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stm.w (lr), [sp-]
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mov ip, #PSR_R_BIT | PSR_I_BIT | PRIV_MODE
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mov.a asr, ip
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b.l __cpuc_flush_kern_all
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ldm.w (pc), [sp]+
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/*
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* cpu_reset(loc)
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*
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* Perform a soft reset of the system. Put the CPU into the
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* same state as it would be if it had been reset, and branch
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* to what would be the reset vector.
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*
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* - loc - location to jump to for soft reset
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*/
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.align 5
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ENTRY(cpu_reset)
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mov ip, #0
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movc p0.c5, ip, #28 @ Cache invalidate all
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nop8
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movc p0.c6, ip, #6 @ TLB invalidate all
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nop8
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movc ip, p0.c1, #0 @ ctrl register
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or ip, ip, #0x2000 @ vector base address
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andn ip, ip, #0x000f @ ............idam
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movc p0.c1, ip, #0 @ disable caches and mmu
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nop
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mov pc, r0 @ jump to loc
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nop8
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/*
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* cpu_do_idle()
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*
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* Idle the processor (eg, wait for interrupt).
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*
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* IRQs are already disabled.
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*/
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ENTRY(cpu_do_idle)
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mov r0, #0 @ PCI address
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.rept 8
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ldw r1, [r0]
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.endr
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mov pc, lr
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ENTRY(cpu_dcache_clean_area)
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#ifndef CONFIG_CPU_DCACHE_LINE_DISABLE
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csub.a r1, #MAX_AREA_SIZE
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bsg 101f
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mov r9, #PAGE_SZ
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sub r9, r9, #1 @ PAGE_MASK
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1: va2pa r0, r10, r11, r12, r13 @ r10 is PA
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b 3f
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2: cand.a r0, r9
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beq 1b
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3: movc p0.c5, r10, #11 @ clean D entry
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nop8
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add r0, r0, #CACHE_LINESIZE
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add r10, r10, #CACHE_LINESIZE
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sub.a r1, r1, #CACHE_LINESIZE
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bua 2b
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mov pc, lr
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#endif
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101: mov ip, #0
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movc p0.c5, ip, #10 @ Dcache clean all
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nop8
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mov pc, lr
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/*
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* cpu_do_switch_mm(pgd_phys)
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*
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* Set the translation table base pointer to be pgd_phys
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*
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* - pgd_phys - physical address of new pgd
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*
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* It is assumed that:
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* - we are not using split page tables
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*/
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.align 5
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ENTRY(cpu_do_switch_mm)
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movc p0.c2, r0, #0 @ update page table ptr
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nop8
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movc p0.c6, ip, #6 @ TLB invalidate all
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nop8
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mov pc, lr
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/*
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* cpu_set_pte(ptep, pte)
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*
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* Set a level 2 translation table entry.
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*
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* - ptep - pointer to level 2 translation table entry
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* - pte - PTE value to store
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*/
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.align 5
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ENTRY(cpu_set_pte)
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stw r1, [r0]
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#ifndef CONFIG_CPU_DCACHE_LINE_DISABLE
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sub r2, r0, #PAGE_OFFSET
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movc p0.c5, r2, #11 @ Dcache clean line
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nop8
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#else
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mov ip, #0
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movc p0.c5, ip, #10 @ Dcache clean all
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nop8
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@dcacheline_flush r0, r2, ip
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#endif
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mov pc, lr
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