360aebd85a
This supports PCI surprise hotplug. The design is highlighted as
below:
* The PCI slot's surprise hotplug capability is exposed through
device node property "ibm,slot-surprise-pluggable", meaning
PCI surprise hotplug will be disabled if skiboot doesn't support
it yet.
* The interrupt because of presence or link state change is raised
on surprise hotplug event. One event is allocated and queued to
the PCI slot for workqueue to pick it up and process in serialized
fashion. The code flow for surprise hotplug is same to that for
managed hotplug except: the affected PEs are put into frozen state
to avoid unexpected EEH error reporting in surprise hot remove path.
Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
81 lines
2.6 KiB
C
81 lines
2.6 KiB
C
/*
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* Copyright 2014 IBM Corp.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#ifndef _ASM_PNV_PCI_H
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#define _ASM_PNV_PCI_H
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#include <linux/pci.h>
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#include <linux/pci_hotplug.h>
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#include <misc/cxl-base.h>
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#include <asm/opal-api.h>
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#define PCI_SLOT_ID_PREFIX 0x8000000000000000
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#define PCI_SLOT_ID(phb_id, bdfn) \
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(PCI_SLOT_ID_PREFIX | ((uint64_t)(bdfn) << 16) | (phb_id))
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extern int pnv_pci_get_slot_id(struct device_node *np, uint64_t *id);
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extern int pnv_pci_get_device_tree(uint32_t phandle, void *buf, uint64_t len);
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extern int pnv_pci_get_presence_state(uint64_t id, uint8_t *state);
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extern int pnv_pci_get_power_state(uint64_t id, uint8_t *state);
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extern int pnv_pci_set_power_state(uint64_t id, uint8_t state,
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struct opal_msg *msg);
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int pnv_phb_to_cxl_mode(struct pci_dev *dev, uint64_t mode);
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int pnv_cxl_ioda_msi_setup(struct pci_dev *dev, unsigned int hwirq,
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unsigned int virq);
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int pnv_cxl_alloc_hwirqs(struct pci_dev *dev, int num);
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void pnv_cxl_release_hwirqs(struct pci_dev *dev, int hwirq, int num);
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int pnv_cxl_get_irq_count(struct pci_dev *dev);
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struct device_node *pnv_pci_get_phb_node(struct pci_dev *dev);
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#ifdef CONFIG_CXL_BASE
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int pnv_cxl_alloc_hwirq_ranges(struct cxl_irq_ranges *irqs,
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struct pci_dev *dev, int num);
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void pnv_cxl_release_hwirq_ranges(struct cxl_irq_ranges *irqs,
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struct pci_dev *dev);
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/* Support for the cxl kernel api on the real PHB (instead of vPHB) */
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int pnv_cxl_enable_phb_kernel_api(struct pci_controller *hose, bool enable);
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bool pnv_pci_on_cxl_phb(struct pci_dev *dev);
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struct cxl_afu *pnv_cxl_phb_to_afu(struct pci_controller *hose);
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void pnv_cxl_phb_set_peer_afu(struct pci_dev *dev, struct cxl_afu *afu);
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#endif
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struct pnv_php_slot {
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struct hotplug_slot slot;
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struct hotplug_slot_info slot_info;
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uint64_t id;
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char *name;
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int slot_no;
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struct kref kref;
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#define PNV_PHP_STATE_INITIALIZED 0
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#define PNV_PHP_STATE_REGISTERED 1
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#define PNV_PHP_STATE_POPULATED 2
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#define PNV_PHP_STATE_OFFLINE 3
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int state;
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int irq;
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struct workqueue_struct *wq;
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struct device_node *dn;
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struct pci_dev *pdev;
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struct pci_bus *bus;
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bool power_state_check;
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void *fdt;
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void *dt;
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struct of_changeset ocs;
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struct pnv_php_slot *parent;
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struct list_head children;
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struct list_head link;
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};
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extern struct pnv_php_slot *pnv_php_find_slot(struct device_node *dn);
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extern int pnv_php_set_slot_power_state(struct hotplug_slot *slot,
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uint8_t state);
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#endif
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