forked from Minki/linux
627988a66a
The patch add two timers to all rk3188 based boards. The first timer is from alive subsystem and it act as a backup for the local timers at sleep time. It act the same as other SoC rockchip timers already present in kernel. The second timer is from CPU subsystem and act as replacement for the arm-global-timer clocksource and sched clock. It run at stable frequency 24MHz. Signed-off-by: Alexander Kochetkov <al.kochet@gmail.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de>
644 lines
15 KiB
Plaintext
644 lines
15 KiB
Plaintext
/*
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* Copyright (c) 2013 MundoReader S.L.
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* Author: Heiko Stuebner <heiko@sntech.de>
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This file is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/pinctrl/rockchip.h>
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#include <dt-bindings/clock/rk3188-cru.h>
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#include "rk3xxx.dtsi"
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/ {
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compatible = "rockchip,rk3188";
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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enable-method = "rockchip,rk3066-smp";
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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next-level-cache = <&L2>;
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reg = <0x0>;
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operating-points = <
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/* kHz uV */
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1608000 1350000
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1416000 1250000
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1200000 1150000
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1008000 1075000
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816000 975000
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600000 950000
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504000 925000
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312000 875000
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>;
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clock-latency = <40000>;
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clocks = <&cru ARMCLK>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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next-level-cache = <&L2>;
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reg = <0x1>;
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};
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cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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next-level-cache = <&L2>;
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reg = <0x2>;
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};
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cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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next-level-cache = <&L2>;
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reg = <0x3>;
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};
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};
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sram: sram@10080000 {
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compatible = "mmio-sram";
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reg = <0x10080000 0x8000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x10080000 0x8000>;
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smp-sram@0 {
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compatible = "rockchip,rk3066-smp-sram";
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reg = <0x0 0x50>;
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};
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};
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timer3: timer@2000e000 {
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compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer";
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reg = <0x2000e000 0x20>;
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interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru SCLK_TIMER3>, <&cru PCLK_TIMER3>;
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clock-names = "timer", "pclk";
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};
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timer6: timer@200380a0 {
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compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer";
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reg = <0x200380a0 0x20>;
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interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru SCLK_TIMER6>, <&cru PCLK_TIMER0>;
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clock-names = "timer", "pclk";
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};
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i2s0: i2s@1011a000 {
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compatible = "rockchip,rk3188-i2s", "rockchip,rk3066-i2s";
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reg = <0x1011a000 0x2000>;
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interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&i2s0_bus>;
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dmas = <&dmac1_s 6>, <&dmac1_s 7>;
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dma-names = "tx", "rx";
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clock-names = "i2s_hclk", "i2s_clk";
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clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
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rockchip,playback-channels = <2>;
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rockchip,capture-channels = <2>;
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status = "disabled";
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};
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spdif: sound@1011e000 {
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compatible = "rockchip,rk3188-spdif", "rockchip,rk3066-spdif";
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reg = <0x1011e000 0x2000>;
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#sound-dai-cells = <0>;
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clock-names = "hclk", "mclk";
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clocks = <&cru HCLK_SPDIF>, <&cru SCLK_SPDIF>;
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dmas = <&dmac1_s 8>;
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dma-names = "tx";
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interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&spdif_tx>;
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status = "disabled";
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};
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cru: clock-controller@20000000 {
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compatible = "rockchip,rk3188-cru";
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reg = <0x20000000 0x1000>;
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rockchip,grf = <&grf>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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efuse: efuse@20010000 {
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compatible = "rockchip,rk3188-efuse";
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reg = <0x20010000 0x4000>;
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#address-cells = <1>;
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#size-cells = <1>;
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clocks = <&cru PCLK_EFUSE>;
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clock-names = "pclk_efuse";
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cpu_leakage: cpu_leakage@17 {
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reg = <0x17 0x1>;
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};
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};
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usbphy: phy {
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compatible = "rockchip,rk3188-usb-phy", "rockchip,rk3288-usb-phy";
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rockchip,grf = <&grf>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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usbphy0: usb-phy@10c {
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#phy-cells = <0>;
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reg = <0x10c>;
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clocks = <&cru SCLK_OTGPHY0>;
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clock-names = "phyclk";
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#clock-cells = <0>;
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};
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usbphy1: usb-phy@11c {
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#phy-cells = <0>;
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reg = <0x11c>;
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clocks = <&cru SCLK_OTGPHY1>;
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clock-names = "phyclk";
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#clock-cells = <0>;
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};
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};
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pinctrl: pinctrl {
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compatible = "rockchip,rk3188-pinctrl";
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rockchip,grf = <&grf>;
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rockchip,pmu = <&pmu>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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gpio0: gpio0@2000a000 {
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compatible = "rockchip,rk3188-gpio-bank0";
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reg = <0x2000a000 0x100>;
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interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru PCLK_GPIO0>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio1: gpio1@2003c000 {
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compatible = "rockchip,gpio-bank";
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reg = <0x2003c000 0x100>;
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interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru PCLK_GPIO1>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio2: gpio2@2003e000 {
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compatible = "rockchip,gpio-bank";
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reg = <0x2003e000 0x100>;
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interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru PCLK_GPIO2>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio3: gpio3@20080000 {
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compatible = "rockchip,gpio-bank";
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reg = <0x20080000 0x100>;
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interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru PCLK_GPIO3>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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pcfg_pull_up: pcfg_pull_up {
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bias-pull-up;
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};
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pcfg_pull_down: pcfg_pull_down {
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bias-pull-down;
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};
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pcfg_pull_none: pcfg_pull_none {
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bias-disable;
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};
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emmc {
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emmc_clk: emmc-clk {
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rockchip,pins = <RK_GPIO0 24 RK_FUNC_2 &pcfg_pull_none>;
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};
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emmc_cmd: emmc-cmd {
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rockchip,pins = <RK_GPIO0 26 RK_FUNC_2 &pcfg_pull_up>;
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};
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emmc_rst: emmc-rst {
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rockchip,pins = <RK_GPIO0 27 RK_FUNC_2 &pcfg_pull_none>;
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};
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/*
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* The data pins are shared between nandc and emmc and
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* not accessible through pinctrl. Also they should've
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* been already set correctly by firmware, as
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* flash/emmc is the boot-device.
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*/
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};
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emac {
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emac_xfer: emac-xfer {
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rockchip,pins = <RK_GPIO3 16 RK_FUNC_2 &pcfg_pull_none>, /* tx_en */
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<RK_GPIO3 17 RK_FUNC_2 &pcfg_pull_none>, /* txd1 */
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<RK_GPIO3 18 RK_FUNC_2 &pcfg_pull_none>, /* txd0 */
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<RK_GPIO3 19 RK_FUNC_2 &pcfg_pull_none>, /* rxd0 */
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<RK_GPIO3 20 RK_FUNC_2 &pcfg_pull_none>, /* rxd1 */
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<RK_GPIO3 21 RK_FUNC_2 &pcfg_pull_none>, /* mac_clk */
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<RK_GPIO3 22 RK_FUNC_2 &pcfg_pull_none>, /* rx_err */
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<RK_GPIO3 23 RK_FUNC_2 &pcfg_pull_none>; /* crs_dvalid */
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};
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emac_mdio: emac-mdio {
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rockchip,pins = <RK_GPIO3 24 RK_FUNC_2 &pcfg_pull_none>,
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<RK_GPIO3 25 RK_FUNC_2 &pcfg_pull_none>;
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};
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};
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i2c0 {
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i2c0_xfer: i2c0-xfer {
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rockchip,pins = <RK_GPIO1 24 RK_FUNC_1 &pcfg_pull_none>,
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<RK_GPIO1 25 RK_FUNC_1 &pcfg_pull_none>;
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};
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};
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i2c1 {
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i2c1_xfer: i2c1-xfer {
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rockchip,pins = <RK_GPIO1 26 RK_FUNC_1 &pcfg_pull_none>,
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<RK_GPIO1 27 RK_FUNC_1 &pcfg_pull_none>;
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};
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};
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i2c2 {
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i2c2_xfer: i2c2-xfer {
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rockchip,pins = <RK_GPIO1 28 RK_FUNC_1 &pcfg_pull_none>,
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<RK_GPIO1 29 RK_FUNC_1 &pcfg_pull_none>;
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};
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};
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i2c3 {
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i2c3_xfer: i2c3-xfer {
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rockchip,pins = <RK_GPIO3 14 RK_FUNC_2 &pcfg_pull_none>,
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<RK_GPIO3 15 RK_FUNC_2 &pcfg_pull_none>;
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};
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};
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i2c4 {
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i2c4_xfer: i2c4-xfer {
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rockchip,pins = <RK_GPIO1 30 RK_FUNC_1 &pcfg_pull_none>,
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<RK_GPIO1 31 RK_FUNC_1 &pcfg_pull_none>;
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};
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};
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pwm0 {
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pwm0_out: pwm0-out {
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rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_none>;
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};
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};
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pwm1 {
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pwm1_out: pwm1-out {
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rockchip,pins = <RK_GPIO3 28 RK_FUNC_1 &pcfg_pull_none>;
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};
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};
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pwm2 {
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pwm2_out: pwm2-out {
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rockchip,pins = <RK_GPIO3 29 RK_FUNC_1 &pcfg_pull_none>;
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};
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};
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pwm3 {
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pwm3_out: pwm3-out {
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rockchip,pins = <RK_GPIO3 30 RK_FUNC_1 &pcfg_pull_none>;
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};
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};
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spi0 {
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spi0_clk: spi0-clk {
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rockchip,pins = <RK_GPIO1 6 RK_FUNC_2 &pcfg_pull_up>;
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};
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spi0_cs0: spi0-cs0 {
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rockchip,pins = <RK_GPIO1 7 RK_FUNC_2 &pcfg_pull_up>;
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};
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spi0_tx: spi0-tx {
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rockchip,pins = <RK_GPIO1 5 RK_FUNC_2 &pcfg_pull_up>;
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};
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spi0_rx: spi0-rx {
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rockchip,pins = <RK_GPIO1 4 RK_FUNC_2 &pcfg_pull_up>;
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};
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spi0_cs1: spi0-cs1 {
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rockchip,pins = <RK_GPIO1 15 RK_FUNC_1 &pcfg_pull_up>;
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};
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};
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spi1 {
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spi1_clk: spi1-clk {
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rockchip,pins = <RK_GPIO0 30 RK_FUNC_1 &pcfg_pull_up>;
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};
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spi1_cs0: spi1-cs0 {
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rockchip,pins = <RK_GPIO0 31 RK_FUNC_1 &pcfg_pull_up>;
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};
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spi1_rx: spi1-rx {
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rockchip,pins = <RK_GPIO0 28 RK_FUNC_1 &pcfg_pull_up>;
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};
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spi1_tx: spi1-tx {
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rockchip,pins = <RK_GPIO0 29 RK_FUNC_1 &pcfg_pull_up>;
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};
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spi1_cs1: spi1-cs1 {
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rockchip,pins = <RK_GPIO1 14 RK_FUNC_2 &pcfg_pull_up>;
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};
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};
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uart0 {
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uart0_xfer: uart0-xfer {
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rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_up>,
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<RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_none>;
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};
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uart0_cts: uart0-cts {
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rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_none>;
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};
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uart0_rts: uart0-rts {
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rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_none>;
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};
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};
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uart1 {
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uart1_xfer: uart1-xfer {
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rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_up>,
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<RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_none>;
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};
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uart1_cts: uart1-cts {
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rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_none>;
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};
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uart1_rts: uart1-rts {
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rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_none>;
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};
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};
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uart2 {
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uart2_xfer: uart2-xfer {
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rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_up>,
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<RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_none>;
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};
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/* no rts / cts for uart2 */
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};
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uart3 {
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uart3_xfer: uart3-xfer {
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rockchip,pins = <RK_GPIO1 10 RK_FUNC_1 &pcfg_pull_up>,
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<RK_GPIO1 11 RK_FUNC_1 &pcfg_pull_none>;
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};
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uart3_cts: uart3-cts {
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rockchip,pins = <RK_GPIO1 12 RK_FUNC_1 &pcfg_pull_none>;
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};
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uart3_rts: uart3-rts {
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rockchip,pins = <RK_GPIO1 13 RK_FUNC_1 &pcfg_pull_none>;
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};
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};
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sd0 {
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sd0_clk: sd0-clk {
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rockchip,pins = <RK_GPIO3 2 RK_FUNC_1 &pcfg_pull_none>;
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};
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sd0_cmd: sd0-cmd {
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rockchip,pins = <RK_GPIO3 3 RK_FUNC_1 &pcfg_pull_none>;
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};
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sd0_cd: sd0-cd {
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rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_none>;
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};
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sd0_wp: sd0-wp {
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rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_none>;
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};
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sd0_pwr: sd0-pwr {
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rockchip,pins = <RK_GPIO3 1 RK_FUNC_1 &pcfg_pull_none>;
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};
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|
|
sd0_bus1: sd0-bus-width1 {
|
|
rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
|
|
sd0_bus4: sd0-bus-width4 {
|
|
rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>,
|
|
<RK_GPIO3 5 RK_FUNC_1 &pcfg_pull_none>,
|
|
<RK_GPIO3 6 RK_FUNC_1 &pcfg_pull_none>,
|
|
<RK_GPIO3 7 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
sd1 {
|
|
sd1_clk: sd1-clk {
|
|
rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
|
|
sd1_cmd: sd1-cmd {
|
|
rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
|
|
sd1_cd: sd1-cd {
|
|
rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
|
|
sd1_wp: sd1-wp {
|
|
rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
|
|
sd1_bus1: sd1-bus-width1 {
|
|
rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
|
|
sd1_bus4: sd1-bus-width4 {
|
|
rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>,
|
|
<RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_none>,
|
|
<RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_none>,
|
|
<RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
i2s0 {
|
|
i2s0_bus: i2s0-bus {
|
|
rockchip,pins = <RK_GPIO1 16 RK_FUNC_1 &pcfg_pull_none>,
|
|
<RK_GPIO1 17 RK_FUNC_1 &pcfg_pull_none>,
|
|
<RK_GPIO1 18 RK_FUNC_1 &pcfg_pull_none>,
|
|
<RK_GPIO1 19 RK_FUNC_1 &pcfg_pull_none>,
|
|
<RK_GPIO1 20 RK_FUNC_1 &pcfg_pull_none>,
|
|
<RK_GPIO1 21 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
spdif {
|
|
spdif_tx: spdif-tx {
|
|
rockchip,pins = <RK_GPIO1 14 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
&emac {
|
|
compatible = "rockchip,rk3188-emac";
|
|
};
|
|
|
|
&global_timer {
|
|
interrupts = <GIC_PPI 11 0xf04>;
|
|
};
|
|
|
|
&local_timer {
|
|
interrupts = <GIC_PPI 13 0xf04>;
|
|
};
|
|
|
|
&i2c0 {
|
|
compatible = "rockchip,rk3188-i2c";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c0_xfer>;
|
|
};
|
|
|
|
&i2c1 {
|
|
compatible = "rockchip,rk3188-i2c";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c1_xfer>;
|
|
};
|
|
|
|
&i2c2 {
|
|
compatible = "rockchip,rk3188-i2c";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c2_xfer>;
|
|
};
|
|
|
|
&i2c3 {
|
|
compatible = "rockchip,rk3188-i2c";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c3_xfer>;
|
|
};
|
|
|
|
&i2c4 {
|
|
compatible = "rockchip,rk3188-i2c";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c4_xfer>;
|
|
};
|
|
|
|
&pwm0 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pwm0_out>;
|
|
};
|
|
|
|
&pwm1 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pwm1_out>;
|
|
};
|
|
|
|
&pwm2 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pwm2_out>;
|
|
};
|
|
|
|
&pwm3 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pwm3_out>;
|
|
};
|
|
|
|
&spi0 {
|
|
compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
|
|
};
|
|
|
|
&spi1 {
|
|
compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
|
|
};
|
|
|
|
&uart0 {
|
|
compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&uart0_xfer>;
|
|
};
|
|
|
|
&uart1 {
|
|
compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&uart1_xfer>;
|
|
};
|
|
|
|
&uart2 {
|
|
compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&uart2_xfer>;
|
|
};
|
|
|
|
&uart3 {
|
|
compatible = "rockchip,rk3188-uart", "snps,dw-apb-uart";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&uart3_xfer>;
|
|
};
|
|
|
|
&wdt {
|
|
compatible = "rockchip,rk3188-wdt", "snps,dw-wdt";
|
|
};
|