9410113fc3
Rationale:
Reduces attack surface on kernel devs opening the links for MITM
as HTTPS traffic is much harder to manipulate.
Deterministic algorithm:
For each file:
If not .svg:
For each line:
If doesn't contain `\bxmlns\b`:
For each link, `\bhttp://[^# \t\r\n]*(?:\w|/)`:
If neither `\bgnu\.org/license`, nor `\bmozilla\.org/MPL\b`:
If both the HTTP and HTTPS versions
return 200 OK and serve the same content:
Replace HTTP with HTTPS.
Signed-off-by: Alexander A. Klimov <grandmaster@al2klimov.de>
Acked-by: Jyri Sarha <jsarha@ti.com>
Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20200713123913.34205-1-grandmaster@al2klimov.de
78 lines
2.3 KiB
C
78 lines
2.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
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* Author: Tomi Valkeinen <tomi.valkeinen@ti.com>
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*/
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#ifndef __TIDSS_IRQ_H__
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#define __TIDSS_IRQ_H__
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#include <linux/types.h>
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#include "tidss_drv.h"
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/*
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* The IRQ status from various DISPC IRQ registers are packed into a single
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* value, where the bits are defined as follows:
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*
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* bit group |dev|wb |mrg0|mrg1|mrg2|mrg3|plane0-3| <unused> |
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* bit use |D |fou|FEOL|FEOL|FEOL|FEOL| UUUU | |
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* bit number|0 |1-3|4-7 |8-11| 12-19 | 20-23 | 24-31 |
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*
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* device bits: D = OCP error
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* WB bits: f = frame done wb, o = wb buffer overflow,
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* u = wb buffer uncomplete
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* vp bits: F = frame done, E = vsync even, O = vsync odd, L = sync lost
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* plane bits: U = fifo underflow
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*/
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#define DSS_IRQ_DEVICE_OCP_ERR BIT(0)
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#define DSS_IRQ_DEVICE_FRAMEDONEWB BIT(1)
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#define DSS_IRQ_DEVICE_WBBUFFEROVERFLOW BIT(2)
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#define DSS_IRQ_DEVICE_WBUNCOMPLETEERROR BIT(3)
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#define DSS_IRQ_DEVICE_WB_MASK GENMASK(3, 1)
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#define DSS_IRQ_VP_BIT_N(ch, bit) (4 + 4 * (ch) + (bit))
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#define DSS_IRQ_PLANE_BIT_N(plane, bit) \
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(DSS_IRQ_VP_BIT_N(TIDSS_MAX_PORTS, 0) + 1 * (plane) + (bit))
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#define DSS_IRQ_VP_BIT(ch, bit) BIT(DSS_IRQ_VP_BIT_N((ch), (bit)))
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#define DSS_IRQ_PLANE_BIT(plane, bit) \
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BIT(DSS_IRQ_PLANE_BIT_N((plane), (bit)))
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static inline dispc_irq_t DSS_IRQ_VP_MASK(u32 ch)
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{
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return GENMASK(DSS_IRQ_VP_BIT_N((ch), 3), DSS_IRQ_VP_BIT_N((ch), 0));
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}
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static inline dispc_irq_t DSS_IRQ_PLANE_MASK(u32 plane)
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{
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return GENMASK(DSS_IRQ_PLANE_BIT_N((plane), 0),
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DSS_IRQ_PLANE_BIT_N((plane), 0));
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}
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#define DSS_IRQ_VP_FRAME_DONE(ch) DSS_IRQ_VP_BIT((ch), 0)
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#define DSS_IRQ_VP_VSYNC_EVEN(ch) DSS_IRQ_VP_BIT((ch), 1)
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#define DSS_IRQ_VP_VSYNC_ODD(ch) DSS_IRQ_VP_BIT((ch), 2)
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#define DSS_IRQ_VP_SYNC_LOST(ch) DSS_IRQ_VP_BIT((ch), 3)
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#define DSS_IRQ_PLANE_FIFO_UNDERFLOW(plane) DSS_IRQ_PLANE_BIT((plane), 0)
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struct drm_crtc;
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struct drm_device;
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struct tidss_device;
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void tidss_irq_enable_vblank(struct drm_crtc *crtc);
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void tidss_irq_disable_vblank(struct drm_crtc *crtc);
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void tidss_irq_preinstall(struct drm_device *ddev);
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int tidss_irq_postinstall(struct drm_device *ddev);
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void tidss_irq_uninstall(struct drm_device *ddev);
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irqreturn_t tidss_irq_handler(int irq, void *arg);
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void tidss_irq_resume(struct tidss_device *tidss);
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#endif
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