234a053824
Update license to use SPDX-License-Identifier instead of verbose license text. Link: http://lkml.kernel.org/r/87d0qgcsz8.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Cc: Rich Felker <dalias@libc.org> Cc: Yoshinori Sato <ysato@users.sourceforge.jp> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
552 lines
15 KiB
C
552 lines
15 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* SH7264 Setup
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*
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* Copyright (C) 2012 Renesas Electronics Europe Ltd
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*/
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#include <linux/platform_device.h>
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#include <linux/init.h>
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#include <linux/serial.h>
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#include <linux/serial_sci.h>
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#include <linux/usb/r8a66597.h>
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#include <linux/sh_timer.h>
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#include <linux/io.h>
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enum {
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UNUSED = 0,
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/* interrupt sources */
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IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
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PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7,
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DMAC0, DMAC1, DMAC2, DMAC3, DMAC4, DMAC5, DMAC6, DMAC7,
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DMAC8, DMAC9, DMAC10, DMAC11, DMAC12, DMAC13, DMAC14, DMAC15,
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USB, VDC3, CMT0, CMT1, BSC, WDT,
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MTU0_ABCD, MTU0_VEF, MTU1_AB, MTU1_VU, MTU2_AB, MTU2_VU,
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MTU3_ABCD, MTU3_TCI3V, MTU4_ABCD, MTU4_TCI4V,
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PWMT1, PWMT2, ADC_ADI,
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SSIF0, SSII1, SSII2, SSII3,
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RSPDIF,
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IIC30, IIC31, IIC32, IIC33,
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SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI,
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SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI,
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SCIF2_BRI, SCIF2_ERI, SCIF2_RXI, SCIF2_TXI,
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SCIF3_BRI, SCIF3_ERI, SCIF3_RXI, SCIF3_TXI,
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SCIF4_BRI, SCIF4_ERI, SCIF4_RXI, SCIF4_TXI,
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SCIF5_BRI, SCIF5_ERI, SCIF5_RXI, SCIF5_TXI,
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SCIF6_BRI, SCIF6_ERI, SCIF6_RXI, SCIF6_TXI,
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SCIF7_BRI, SCIF7_ERI, SCIF7_RXI, SCIF7_TXI,
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SIO_FIFO, RSPIC0, RSPIC1,
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RCAN0, RCAN1, IEBC, CD_ROMD,
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NFMC, SDHI, RTC,
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SRCC0, SRCC1, DCOMU, OFFI, IFEI,
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/* interrupt groups */
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PINT, SCIF0, SCIF1, SCIF2, SCIF3, SCIF4, SCIF5, SCIF6, SCIF7,
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};
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static struct intc_vect vectors[] __initdata = {
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INTC_IRQ(IRQ0, 64), INTC_IRQ(IRQ1, 65),
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INTC_IRQ(IRQ2, 66), INTC_IRQ(IRQ3, 67),
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INTC_IRQ(IRQ4, 68), INTC_IRQ(IRQ5, 69),
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INTC_IRQ(IRQ6, 70), INTC_IRQ(IRQ7, 71),
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INTC_IRQ(PINT0, 80), INTC_IRQ(PINT1, 81),
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INTC_IRQ(PINT2, 82), INTC_IRQ(PINT3, 83),
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INTC_IRQ(PINT4, 84), INTC_IRQ(PINT5, 85),
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INTC_IRQ(PINT6, 86), INTC_IRQ(PINT7, 87),
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INTC_IRQ(DMAC0, 108), INTC_IRQ(DMAC0, 109),
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INTC_IRQ(DMAC1, 112), INTC_IRQ(DMAC1, 113),
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INTC_IRQ(DMAC2, 116), INTC_IRQ(DMAC2, 117),
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INTC_IRQ(DMAC3, 120), INTC_IRQ(DMAC3, 121),
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INTC_IRQ(DMAC4, 124), INTC_IRQ(DMAC4, 125),
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INTC_IRQ(DMAC5, 128), INTC_IRQ(DMAC5, 129),
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INTC_IRQ(DMAC6, 132), INTC_IRQ(DMAC6, 133),
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INTC_IRQ(DMAC7, 136), INTC_IRQ(DMAC7, 137),
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INTC_IRQ(DMAC8, 140), INTC_IRQ(DMAC8, 141),
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INTC_IRQ(DMAC9, 144), INTC_IRQ(DMAC9, 145),
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INTC_IRQ(DMAC10, 148), INTC_IRQ(DMAC10, 149),
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INTC_IRQ(DMAC11, 152), INTC_IRQ(DMAC11, 153),
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INTC_IRQ(DMAC12, 156), INTC_IRQ(DMAC12, 157),
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INTC_IRQ(DMAC13, 160), INTC_IRQ(DMAC13, 161),
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INTC_IRQ(DMAC14, 164), INTC_IRQ(DMAC14, 165),
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INTC_IRQ(DMAC15, 168), INTC_IRQ(DMAC15, 169),
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INTC_IRQ(USB, 170),
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INTC_IRQ(VDC3, 171), INTC_IRQ(VDC3, 172),
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INTC_IRQ(VDC3, 173), INTC_IRQ(VDC3, 174),
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INTC_IRQ(CMT0, 175), INTC_IRQ(CMT1, 176),
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INTC_IRQ(BSC, 177), INTC_IRQ(WDT, 178),
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INTC_IRQ(MTU0_ABCD, 179), INTC_IRQ(MTU0_ABCD, 180),
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INTC_IRQ(MTU0_ABCD, 181), INTC_IRQ(MTU0_ABCD, 182),
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INTC_IRQ(MTU0_VEF, 183),
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INTC_IRQ(MTU0_VEF, 184), INTC_IRQ(MTU0_VEF, 185),
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INTC_IRQ(MTU1_AB, 186), INTC_IRQ(MTU1_AB, 187),
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INTC_IRQ(MTU1_VU, 188), INTC_IRQ(MTU1_VU, 189),
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INTC_IRQ(MTU2_AB, 190), INTC_IRQ(MTU2_AB, 191),
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INTC_IRQ(MTU2_VU, 192), INTC_IRQ(MTU2_VU, 193),
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INTC_IRQ(MTU3_ABCD, 194), INTC_IRQ(MTU3_ABCD, 195),
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INTC_IRQ(MTU3_ABCD, 196), INTC_IRQ(MTU3_ABCD, 197),
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INTC_IRQ(MTU3_TCI3V, 198),
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INTC_IRQ(MTU4_ABCD, 199), INTC_IRQ(MTU4_ABCD, 200),
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INTC_IRQ(MTU4_ABCD, 201), INTC_IRQ(MTU4_ABCD, 202),
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INTC_IRQ(MTU4_TCI4V, 203),
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INTC_IRQ(PWMT1, 204), INTC_IRQ(PWMT2, 205),
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INTC_IRQ(ADC_ADI, 206),
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INTC_IRQ(SSIF0, 207), INTC_IRQ(SSIF0, 208),
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INTC_IRQ(SSIF0, 209),
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INTC_IRQ(SSII1, 210), INTC_IRQ(SSII1, 211),
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INTC_IRQ(SSII2, 212), INTC_IRQ(SSII2, 213),
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INTC_IRQ(SSII3, 214), INTC_IRQ(SSII3, 215),
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INTC_IRQ(RSPDIF, 216),
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INTC_IRQ(IIC30, 217), INTC_IRQ(IIC30, 218),
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INTC_IRQ(IIC30, 219), INTC_IRQ(IIC30, 220),
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INTC_IRQ(IIC30, 221),
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INTC_IRQ(IIC31, 222), INTC_IRQ(IIC31, 223),
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INTC_IRQ(IIC31, 224), INTC_IRQ(IIC31, 225),
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INTC_IRQ(IIC31, 226),
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INTC_IRQ(IIC32, 227), INTC_IRQ(IIC32, 228),
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INTC_IRQ(IIC32, 229), INTC_IRQ(IIC32, 230),
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INTC_IRQ(IIC32, 231),
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INTC_IRQ(SCIF0_BRI, 232), INTC_IRQ(SCIF0_ERI, 233),
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INTC_IRQ(SCIF0_RXI, 234), INTC_IRQ(SCIF0_TXI, 235),
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INTC_IRQ(SCIF1_BRI, 236), INTC_IRQ(SCIF1_ERI, 237),
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INTC_IRQ(SCIF1_RXI, 238), INTC_IRQ(SCIF1_TXI, 239),
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INTC_IRQ(SCIF2_BRI, 240), INTC_IRQ(SCIF2_ERI, 241),
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INTC_IRQ(SCIF2_RXI, 242), INTC_IRQ(SCIF2_TXI, 243),
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INTC_IRQ(SCIF3_BRI, 244), INTC_IRQ(SCIF3_ERI, 245),
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INTC_IRQ(SCIF3_RXI, 246), INTC_IRQ(SCIF3_TXI, 247),
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INTC_IRQ(SCIF4_BRI, 248), INTC_IRQ(SCIF4_ERI, 249),
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INTC_IRQ(SCIF4_RXI, 250), INTC_IRQ(SCIF4_TXI, 251),
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INTC_IRQ(SCIF5_BRI, 252), INTC_IRQ(SCIF5_ERI, 253),
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INTC_IRQ(SCIF5_RXI, 254), INTC_IRQ(SCIF5_TXI, 255),
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INTC_IRQ(SCIF6_BRI, 256), INTC_IRQ(SCIF6_ERI, 257),
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INTC_IRQ(SCIF6_RXI, 258), INTC_IRQ(SCIF6_TXI, 259),
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INTC_IRQ(SCIF7_BRI, 260), INTC_IRQ(SCIF7_ERI, 261),
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INTC_IRQ(SCIF7_RXI, 262), INTC_IRQ(SCIF7_TXI, 263),
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INTC_IRQ(SIO_FIFO, 264),
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INTC_IRQ(RSPIC0, 265), INTC_IRQ(RSPIC0, 266),
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INTC_IRQ(RSPIC0, 267),
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INTC_IRQ(RSPIC1, 268), INTC_IRQ(RSPIC1, 269),
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INTC_IRQ(RSPIC1, 270),
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INTC_IRQ(RCAN0, 271), INTC_IRQ(RCAN0, 272),
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INTC_IRQ(RCAN0, 273), INTC_IRQ(RCAN0, 274),
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INTC_IRQ(RCAN0, 275),
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INTC_IRQ(RCAN1, 276), INTC_IRQ(RCAN1, 277),
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INTC_IRQ(RCAN1, 278), INTC_IRQ(RCAN1, 279),
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INTC_IRQ(RCAN1, 280),
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INTC_IRQ(IEBC, 281),
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INTC_IRQ(CD_ROMD, 282), INTC_IRQ(CD_ROMD, 283),
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INTC_IRQ(CD_ROMD, 284), INTC_IRQ(CD_ROMD, 285),
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INTC_IRQ(CD_ROMD, 286), INTC_IRQ(CD_ROMD, 287),
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INTC_IRQ(NFMC, 288), INTC_IRQ(NFMC, 289),
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INTC_IRQ(NFMC, 290), INTC_IRQ(NFMC, 291),
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INTC_IRQ(SDHI, 292), INTC_IRQ(SDHI, 293),
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INTC_IRQ(SDHI, 294),
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INTC_IRQ(RTC, 296), INTC_IRQ(RTC, 297),
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INTC_IRQ(RTC, 298),
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INTC_IRQ(SRCC0, 299), INTC_IRQ(SRCC0, 300),
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INTC_IRQ(SRCC0, 301), INTC_IRQ(SRCC0, 302),
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INTC_IRQ(SRCC0, 303),
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INTC_IRQ(SRCC1, 304), INTC_IRQ(SRCC1, 305),
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INTC_IRQ(SRCC1, 306), INTC_IRQ(SRCC1, 307),
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INTC_IRQ(SRCC1, 308),
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INTC_IRQ(DCOMU, 310), INTC_IRQ(DCOMU, 311),
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INTC_IRQ(DCOMU, 312),
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};
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static struct intc_group groups[] __initdata = {
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INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3,
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PINT4, PINT5, PINT6, PINT7),
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INTC_GROUP(SCIF0, SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI),
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INTC_GROUP(SCIF1, SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI),
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INTC_GROUP(SCIF2, SCIF2_BRI, SCIF2_ERI, SCIF2_RXI, SCIF2_TXI),
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INTC_GROUP(SCIF3, SCIF3_BRI, SCIF3_ERI, SCIF3_RXI, SCIF3_TXI),
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INTC_GROUP(SCIF4, SCIF4_BRI, SCIF4_ERI, SCIF4_RXI, SCIF4_TXI),
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INTC_GROUP(SCIF5, SCIF5_BRI, SCIF5_ERI, SCIF5_RXI, SCIF5_TXI),
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INTC_GROUP(SCIF6, SCIF6_BRI, SCIF6_ERI, SCIF6_RXI, SCIF6_TXI),
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INTC_GROUP(SCIF7, SCIF7_BRI, SCIF7_ERI, SCIF7_RXI, SCIF7_TXI),
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};
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static struct intc_prio_reg prio_registers[] __initdata = {
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{ 0xfffe0818, 0, 16, 4, /* IPR01 */ { IRQ0, IRQ1, IRQ2, IRQ3 } },
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{ 0xfffe081a, 0, 16, 4, /* IPR02 */ { IRQ4, IRQ5, IRQ6, IRQ7 } },
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{ 0xfffe0820, 0, 16, 4, /* IPR05 */ { PINT, 0, 0, 0 } },
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{ 0xfffe0c00, 0, 16, 4, /* IPR06 */ { DMAC0, DMAC1, DMAC2, DMAC3 } },
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{ 0xfffe0c02, 0, 16, 4, /* IPR07 */ { DMAC4, DMAC5, DMAC6, DMAC7 } },
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{ 0xfffe0c04, 0, 16, 4, /* IPR08 */ { DMAC8, DMAC9,
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DMAC10, DMAC11 } },
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{ 0xfffe0c06, 0, 16, 4, /* IPR09 */ { DMAC12, DMAC13,
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DMAC14, DMAC15 } },
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{ 0xfffe0c08, 0, 16, 4, /* IPR10 */ { USB, VDC3, CMT0, CMT1 } },
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{ 0xfffe0c0a, 0, 16, 4, /* IPR11 */ { BSC, WDT, MTU0_ABCD, MTU0_VEF } },
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{ 0xfffe0c0c, 0, 16, 4, /* IPR12 */ { MTU1_AB, MTU1_VU,
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MTU2_AB, MTU2_VU } },
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{ 0xfffe0c0e, 0, 16, 4, /* IPR13 */ { MTU3_ABCD, MTU3_TCI3V,
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MTU4_ABCD, MTU4_TCI4V } },
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{ 0xfffe0c10, 0, 16, 4, /* IPR14 */ { PWMT1, PWMT2, ADC_ADI, 0 } },
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{ 0xfffe0c12, 0, 16, 4, /* IPR15 */ { SSIF0, SSII1, SSII2, SSII3 } },
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{ 0xfffe0c14, 0, 16, 4, /* IPR16 */ { RSPDIF, IIC30, IIC31, IIC32 } },
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{ 0xfffe0c16, 0, 16, 4, /* IPR17 */ { SCIF0, SCIF1, SCIF2, SCIF3 } },
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{ 0xfffe0c18, 0, 16, 4, /* IPR18 */ { SCIF4, SCIF5, SCIF6, SCIF7 } },
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{ 0xfffe0c1a, 0, 16, 4, /* IPR19 */ { SIO_FIFO, 0, RSPIC0, RSPIC1, } },
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{ 0xfffe0c1c, 0, 16, 4, /* IPR20 */ { RCAN0, RCAN1, IEBC, CD_ROMD } },
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{ 0xfffe0c1e, 0, 16, 4, /* IPR21 */ { NFMC, SDHI, RTC, 0 } },
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{ 0xfffe0c20, 0, 16, 4, /* IPR22 */ { SRCC0, SRCC1, 0, DCOMU } },
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};
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static struct intc_mask_reg mask_registers[] __initdata = {
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{ 0xfffe0808, 0, 16, /* PINTER */
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{ 0, 0, 0, 0, 0, 0, 0, 0,
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PINT7, PINT6, PINT5, PINT4, PINT3, PINT2, PINT1, PINT0 } },
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};
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static DECLARE_INTC_DESC(intc_desc, "sh7264", vectors, groups,
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mask_registers, prio_registers, NULL);
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static struct plat_sci_port scif0_platform_data = {
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.scscr = SCSCR_REIE,
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.type = PORT_SCIF,
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.regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
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};
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static struct resource scif0_resources[] = {
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DEFINE_RES_MEM(0xfffe8000, 0x100),
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DEFINE_RES_IRQ(233),
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DEFINE_RES_IRQ(234),
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DEFINE_RES_IRQ(235),
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DEFINE_RES_IRQ(232),
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};
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static struct platform_device scif0_device = {
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.name = "sh-sci",
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.id = 0,
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.resource = scif0_resources,
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.num_resources = ARRAY_SIZE(scif0_resources),
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.dev = {
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.platform_data = &scif0_platform_data,
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},
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};
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static struct plat_sci_port scif1_platform_data = {
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.scscr = SCSCR_REIE,
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.type = PORT_SCIF,
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.regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
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};
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static struct resource scif1_resources[] = {
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DEFINE_RES_MEM(0xfffe8800, 0x100),
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DEFINE_RES_IRQ(237),
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DEFINE_RES_IRQ(238),
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DEFINE_RES_IRQ(239),
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DEFINE_RES_IRQ(236),
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};
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static struct platform_device scif1_device = {
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.name = "sh-sci",
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.id = 1,
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.resource = scif1_resources,
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.num_resources = ARRAY_SIZE(scif1_resources),
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.dev = {
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.platform_data = &scif1_platform_data,
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},
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};
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static struct plat_sci_port scif2_platform_data = {
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.scscr = SCSCR_REIE,
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.type = PORT_SCIF,
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.regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
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};
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static struct resource scif2_resources[] = {
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DEFINE_RES_MEM(0xfffe9000, 0x100),
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DEFINE_RES_IRQ(241),
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DEFINE_RES_IRQ(242),
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DEFINE_RES_IRQ(243),
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DEFINE_RES_IRQ(240),
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};
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static struct platform_device scif2_device = {
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.name = "sh-sci",
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.id = 2,
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.resource = scif2_resources,
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.num_resources = ARRAY_SIZE(scif2_resources),
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.dev = {
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.platform_data = &scif2_platform_data,
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},
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};
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static struct plat_sci_port scif3_platform_data = {
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.scscr = SCSCR_REIE,
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.type = PORT_SCIF,
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.regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
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};
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static struct resource scif3_resources[] = {
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DEFINE_RES_MEM(0xfffe9800, 0x100),
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DEFINE_RES_IRQ(245),
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DEFINE_RES_IRQ(246),
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DEFINE_RES_IRQ(247),
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DEFINE_RES_IRQ(244),
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};
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static struct platform_device scif3_device = {
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.name = "sh-sci",
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.id = 3,
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.resource = scif3_resources,
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.num_resources = ARRAY_SIZE(scif3_resources),
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.dev = {
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.platform_data = &scif3_platform_data,
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},
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};
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static struct plat_sci_port scif4_platform_data = {
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.scscr = SCSCR_REIE,
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.type = PORT_SCIF,
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.regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
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};
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static struct resource scif4_resources[] = {
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DEFINE_RES_MEM(0xfffea000, 0x100),
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DEFINE_RES_IRQ(249),
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DEFINE_RES_IRQ(250),
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DEFINE_RES_IRQ(251),
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DEFINE_RES_IRQ(248),
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};
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static struct platform_device scif4_device = {
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.name = "sh-sci",
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.id = 4,
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.resource = scif4_resources,
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.num_resources = ARRAY_SIZE(scif4_resources),
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.dev = {
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.platform_data = &scif4_platform_data,
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},
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};
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static struct plat_sci_port scif5_platform_data = {
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.scscr = SCSCR_REIE,
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.type = PORT_SCIF,
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.regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
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};
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static struct resource scif5_resources[] = {
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DEFINE_RES_MEM(0xfffea800, 0x100),
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DEFINE_RES_IRQ(253),
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DEFINE_RES_IRQ(254),
|
|
DEFINE_RES_IRQ(255),
|
|
DEFINE_RES_IRQ(252),
|
|
};
|
|
|
|
static struct platform_device scif5_device = {
|
|
.name = "sh-sci",
|
|
.id = 5,
|
|
.resource = scif5_resources,
|
|
.num_resources = ARRAY_SIZE(scif5_resources),
|
|
.dev = {
|
|
.platform_data = &scif5_platform_data,
|
|
},
|
|
};
|
|
|
|
static struct plat_sci_port scif6_platform_data = {
|
|
.scscr = SCSCR_REIE,
|
|
.type = PORT_SCIF,
|
|
.regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
|
|
};
|
|
|
|
static struct resource scif6_resources[] = {
|
|
DEFINE_RES_MEM(0xfffeb000, 0x100),
|
|
DEFINE_RES_IRQ(257),
|
|
DEFINE_RES_IRQ(258),
|
|
DEFINE_RES_IRQ(259),
|
|
DEFINE_RES_IRQ(256),
|
|
};
|
|
|
|
static struct platform_device scif6_device = {
|
|
.name = "sh-sci",
|
|
.id = 6,
|
|
.resource = scif6_resources,
|
|
.num_resources = ARRAY_SIZE(scif6_resources),
|
|
.dev = {
|
|
.platform_data = &scif6_platform_data,
|
|
},
|
|
};
|
|
|
|
static struct plat_sci_port scif7_platform_data = {
|
|
.scscr = SCSCR_REIE,
|
|
.type = PORT_SCIF,
|
|
.regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
|
|
};
|
|
|
|
static struct resource scif7_resources[] = {
|
|
DEFINE_RES_MEM(0xfffeb800, 0x100),
|
|
DEFINE_RES_IRQ(261),
|
|
DEFINE_RES_IRQ(262),
|
|
DEFINE_RES_IRQ(263),
|
|
DEFINE_RES_IRQ(260),
|
|
};
|
|
|
|
static struct platform_device scif7_device = {
|
|
.name = "sh-sci",
|
|
.id = 7,
|
|
.resource = scif7_resources,
|
|
.num_resources = ARRAY_SIZE(scif7_resources),
|
|
.dev = {
|
|
.platform_data = &scif7_platform_data,
|
|
},
|
|
};
|
|
|
|
static struct sh_timer_config cmt_platform_data = {
|
|
.channels_mask = 3,
|
|
};
|
|
|
|
static struct resource cmt_resources[] = {
|
|
DEFINE_RES_MEM(0xfffec000, 0x10),
|
|
DEFINE_RES_IRQ(175),
|
|
DEFINE_RES_IRQ(176),
|
|
};
|
|
|
|
static struct platform_device cmt_device = {
|
|
.name = "sh-cmt-16",
|
|
.id = 0,
|
|
.dev = {
|
|
.platform_data = &cmt_platform_data,
|
|
},
|
|
.resource = cmt_resources,
|
|
.num_resources = ARRAY_SIZE(cmt_resources),
|
|
};
|
|
|
|
static struct resource mtu2_resources[] = {
|
|
DEFINE_RES_MEM(0xfffe4000, 0x400),
|
|
DEFINE_RES_IRQ_NAMED(179, "tgi0a"),
|
|
DEFINE_RES_IRQ_NAMED(186, "tgi1a"),
|
|
};
|
|
|
|
static struct platform_device mtu2_device = {
|
|
.name = "sh-mtu2",
|
|
.id = -1,
|
|
.resource = mtu2_resources,
|
|
.num_resources = ARRAY_SIZE(mtu2_resources),
|
|
};
|
|
|
|
static struct resource rtc_resources[] = {
|
|
[0] = {
|
|
.start = 0xfffe6000,
|
|
.end = 0xfffe6000 + 0x30 - 1,
|
|
.flags = IORESOURCE_IO,
|
|
},
|
|
[1] = {
|
|
/* Shared Period/Carry/Alarm IRQ */
|
|
.start = 296,
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
};
|
|
|
|
static struct platform_device rtc_device = {
|
|
.name = "sh-rtc",
|
|
.id = -1,
|
|
.num_resources = ARRAY_SIZE(rtc_resources),
|
|
.resource = rtc_resources,
|
|
};
|
|
|
|
/* USB Host */
|
|
static void usb_port_power(int port, int power)
|
|
{
|
|
__raw_writew(0x200 , 0xffffc0c2) ; /* Initialise UACS25 */
|
|
}
|
|
|
|
static struct r8a66597_platdata r8a66597_data = {
|
|
.on_chip = 1,
|
|
.endian = 1,
|
|
.port_power = usb_port_power,
|
|
};
|
|
|
|
static struct resource r8a66597_usb_host_resources[] = {
|
|
[0] = {
|
|
.start = 0xffffc000,
|
|
.end = 0xffffc0e4,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
[1] = {
|
|
.start = 170,
|
|
.end = 170,
|
|
.flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
|
|
},
|
|
};
|
|
|
|
static struct platform_device r8a66597_usb_host_device = {
|
|
.name = "r8a66597_hcd",
|
|
.id = 0,
|
|
.dev = {
|
|
.dma_mask = NULL, /* not use dma */
|
|
.coherent_dma_mask = 0xffffffff,
|
|
.platform_data = &r8a66597_data,
|
|
},
|
|
.num_resources = ARRAY_SIZE(r8a66597_usb_host_resources),
|
|
.resource = r8a66597_usb_host_resources,
|
|
};
|
|
|
|
static struct platform_device *sh7264_devices[] __initdata = {
|
|
&scif0_device,
|
|
&scif1_device,
|
|
&scif2_device,
|
|
&scif3_device,
|
|
&scif4_device,
|
|
&scif5_device,
|
|
&scif6_device,
|
|
&scif7_device,
|
|
&cmt_device,
|
|
&mtu2_device,
|
|
&rtc_device,
|
|
&r8a66597_usb_host_device,
|
|
};
|
|
|
|
static int __init sh7264_devices_setup(void)
|
|
{
|
|
return platform_add_devices(sh7264_devices,
|
|
ARRAY_SIZE(sh7264_devices));
|
|
}
|
|
arch_initcall(sh7264_devices_setup);
|
|
|
|
void __init plat_irq_setup(void)
|
|
{
|
|
register_intc_controller(&intc_desc);
|
|
}
|
|
|
|
static struct platform_device *sh7264_early_devices[] __initdata = {
|
|
&scif0_device,
|
|
&scif1_device,
|
|
&scif2_device,
|
|
&scif3_device,
|
|
&scif4_device,
|
|
&scif5_device,
|
|
&scif6_device,
|
|
&scif7_device,
|
|
&cmt_device,
|
|
&mtu2_device,
|
|
};
|
|
|
|
void __init plat_early_device_setup(void)
|
|
{
|
|
early_platform_add_devices(sh7264_early_devices,
|
|
ARRAY_SIZE(sh7264_early_devices));
|
|
}
|