65ae8d2621
Hardcode the absence of the MIPS16e2 ASE for all the systems that do so for the MIPS16 ASE already, providing for code to be optimized away. Signed-off-by: Maciej W. Rozycki <macro@imgtec.com> Reviewed-by: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/16097/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
66 lines
1.6 KiB
C
66 lines
1.6 KiB
C
/*
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* Atheros AR231x/AR531x SoC specific CPU feature overrides
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*
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* Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
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*
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* This file was derived from: include/asm-mips/cpu-features.h
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* Copyright (C) 2003, 2004 Ralf Baechle
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* Copyright (C) 2004 Maciej W. Rozycki
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*
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*/
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#ifndef __ASM_MACH_ATH25_CPU_FEATURE_OVERRIDES_H
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#define __ASM_MACH_ATH25_CPU_FEATURE_OVERRIDES_H
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/*
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* The Atheros AR531x/AR231x SoCs have MIPS 4Kc/4KEc core.
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*/
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#define cpu_has_tlb 1
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#define cpu_has_4kex 1
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#define cpu_has_3k_cache 0
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#define cpu_has_4k_cache 1
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#define cpu_has_tx39_cache 0
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#define cpu_has_sb1_cache 0
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#define cpu_has_fpu 0
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#define cpu_has_32fpr 0
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#define cpu_has_counter 1
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#define cpu_has_ejtag 1
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#if !defined(CONFIG_SOC_AR5312)
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# define cpu_has_llsc 1
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#else
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/*
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* The MIPS 4Kc V0.9 core in the AR5312/AR2312 have problems with the
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* ll/sc instructions.
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*/
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# define cpu_has_llsc 0
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#endif
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#define cpu_has_mips16 0
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#define cpu_has_mips16e2 0
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#define cpu_has_mdmx 0
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#define cpu_has_mips3d 0
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#define cpu_has_smartmips 0
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#define cpu_has_mips32r1 1
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#if !defined(CONFIG_SOC_AR5312)
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# define cpu_has_mips32r2 1
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#endif
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#define cpu_has_mips64r1 0
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#define cpu_has_mips64r2 0
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#define cpu_has_dsp 0
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#define cpu_has_mipsmt 0
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#define cpu_has_64bits 0
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#define cpu_has_64bit_zero_reg 0
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#define cpu_has_64bit_gp_regs 0
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#define cpu_has_64bit_addresses 0
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#endif /* __ASM_MACH_ATH25_CPU_FEATURE_OVERRIDES_H */
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