forked from Minki/linux
77adf3f01b
All files in this driver directory contain the following notice:
See LICENSE.qla2xxx for copyright and licensing details.
LICENSE.qla2xxx can be found in Documentation/scsi/. The file contains:
- A copyright notice
This copyright notice is redundant as all files contain the same
copyright notice already
- A license notice
You may modify and redistribute the device driver code under the
GNU General Public License (a copy of which is attached hereto as
Exhibit A) published by the Free Software Foundation (version 2).
This can be replaced with the corresponding SPDX license identifier
(GPL-2.0-only) in the source files which reference this license
file.
- The full GPLv2 license text
A redundant copy of LICENSES/preferred/GPL-2.0
Remove the notices and add the SPDX license identifier GPL-2.0-only to the
source files.
Finally remove the now redundant LICENSE.qla2xxx file.
Reviewed-by: Richard Fontana <rfontana@redhat.com>
Reviewed-by: Jilayne Lovejoy <opensource@jilayne.com>
Reviewed-by: Alexios Zavras <alexios.zavras@intel.com>
Acked-by: Igor Russkikh <irusskikh@marvell.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Lukas Bulwahn <lukas.bulwahn@gmail.com>
Acked-by: Nilesh Javali <njavali@marvell.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
387 lines
9.8 KiB
C
387 lines
9.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* QLogic Fibre Channel HBA Driver
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* Copyright (c) 2003-2014 QLogic Corporation
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*/
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#include "qla_def.h"
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/*
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* Firmware Dump structure definition
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*/
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struct qla2300_fw_dump {
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__be16 hccr;
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__be16 pbiu_reg[8];
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__be16 risc_host_reg[8];
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__be16 mailbox_reg[32];
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__be16 resp_dma_reg[32];
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__be16 dma_reg[48];
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__be16 risc_hdw_reg[16];
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__be16 risc_gp0_reg[16];
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__be16 risc_gp1_reg[16];
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__be16 risc_gp2_reg[16];
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__be16 risc_gp3_reg[16];
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__be16 risc_gp4_reg[16];
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__be16 risc_gp5_reg[16];
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__be16 risc_gp6_reg[16];
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__be16 risc_gp7_reg[16];
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__be16 frame_buf_hdw_reg[64];
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__be16 fpm_b0_reg[64];
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__be16 fpm_b1_reg[64];
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__be16 risc_ram[0xf800];
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__be16 stack_ram[0x1000];
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__be16 data_ram[1];
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};
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struct qla2100_fw_dump {
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__be16 hccr;
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__be16 pbiu_reg[8];
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__be16 mailbox_reg[32];
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__be16 dma_reg[48];
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__be16 risc_hdw_reg[16];
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__be16 risc_gp0_reg[16];
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__be16 risc_gp1_reg[16];
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__be16 risc_gp2_reg[16];
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__be16 risc_gp3_reg[16];
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__be16 risc_gp4_reg[16];
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__be16 risc_gp5_reg[16];
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__be16 risc_gp6_reg[16];
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__be16 risc_gp7_reg[16];
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__be16 frame_buf_hdw_reg[16];
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__be16 fpm_b0_reg[64];
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__be16 fpm_b1_reg[64];
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__be16 risc_ram[0xf000];
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u8 queue_dump[];
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};
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struct qla24xx_fw_dump {
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__be32 host_status;
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__be32 host_reg[32];
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__be32 shadow_reg[7];
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__be16 mailbox_reg[32];
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__be32 xseq_gp_reg[128];
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__be32 xseq_0_reg[16];
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__be32 xseq_1_reg[16];
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__be32 rseq_gp_reg[128];
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__be32 rseq_0_reg[16];
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__be32 rseq_1_reg[16];
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__be32 rseq_2_reg[16];
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__be32 cmd_dma_reg[16];
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__be32 req0_dma_reg[15];
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__be32 resp0_dma_reg[15];
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__be32 req1_dma_reg[15];
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__be32 xmt0_dma_reg[32];
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__be32 xmt1_dma_reg[32];
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__be32 xmt2_dma_reg[32];
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__be32 xmt3_dma_reg[32];
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__be32 xmt4_dma_reg[32];
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__be32 xmt_data_dma_reg[16];
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__be32 rcvt0_data_dma_reg[32];
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__be32 rcvt1_data_dma_reg[32];
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__be32 risc_gp_reg[128];
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__be32 lmc_reg[112];
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__be32 fpm_hdw_reg[192];
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__be32 fb_hdw_reg[176];
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__be32 code_ram[0x2000];
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__be32 ext_mem[1];
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};
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struct qla25xx_fw_dump {
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__be32 host_status;
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__be32 host_risc_reg[32];
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__be32 pcie_regs[4];
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__be32 host_reg[32];
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__be32 shadow_reg[11];
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__be32 risc_io_reg;
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__be16 mailbox_reg[32];
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__be32 xseq_gp_reg[128];
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__be32 xseq_0_reg[48];
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__be32 xseq_1_reg[16];
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__be32 rseq_gp_reg[128];
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__be32 rseq_0_reg[32];
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__be32 rseq_1_reg[16];
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__be32 rseq_2_reg[16];
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__be32 aseq_gp_reg[128];
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__be32 aseq_0_reg[32];
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__be32 aseq_1_reg[16];
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__be32 aseq_2_reg[16];
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__be32 cmd_dma_reg[16];
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__be32 req0_dma_reg[15];
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__be32 resp0_dma_reg[15];
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__be32 req1_dma_reg[15];
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__be32 xmt0_dma_reg[32];
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__be32 xmt1_dma_reg[32];
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__be32 xmt2_dma_reg[32];
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__be32 xmt3_dma_reg[32];
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__be32 xmt4_dma_reg[32];
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__be32 xmt_data_dma_reg[16];
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__be32 rcvt0_data_dma_reg[32];
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__be32 rcvt1_data_dma_reg[32];
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__be32 risc_gp_reg[128];
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__be32 lmc_reg[128];
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__be32 fpm_hdw_reg[192];
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__be32 fb_hdw_reg[192];
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__be32 code_ram[0x2000];
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__be32 ext_mem[1];
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};
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struct qla81xx_fw_dump {
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__be32 host_status;
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__be32 host_risc_reg[32];
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__be32 pcie_regs[4];
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__be32 host_reg[32];
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__be32 shadow_reg[11];
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__be32 risc_io_reg;
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__be16 mailbox_reg[32];
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__be32 xseq_gp_reg[128];
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__be32 xseq_0_reg[48];
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__be32 xseq_1_reg[16];
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__be32 rseq_gp_reg[128];
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__be32 rseq_0_reg[32];
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__be32 rseq_1_reg[16];
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__be32 rseq_2_reg[16];
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__be32 aseq_gp_reg[128];
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__be32 aseq_0_reg[32];
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__be32 aseq_1_reg[16];
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__be32 aseq_2_reg[16];
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__be32 cmd_dma_reg[16];
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__be32 req0_dma_reg[15];
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__be32 resp0_dma_reg[15];
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__be32 req1_dma_reg[15];
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__be32 xmt0_dma_reg[32];
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__be32 xmt1_dma_reg[32];
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__be32 xmt2_dma_reg[32];
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__be32 xmt3_dma_reg[32];
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__be32 xmt4_dma_reg[32];
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__be32 xmt_data_dma_reg[16];
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__be32 rcvt0_data_dma_reg[32];
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__be32 rcvt1_data_dma_reg[32];
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__be32 risc_gp_reg[128];
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__be32 lmc_reg[128];
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__be32 fpm_hdw_reg[224];
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__be32 fb_hdw_reg[208];
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__be32 code_ram[0x2000];
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__be32 ext_mem[1];
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};
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struct qla83xx_fw_dump {
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__be32 host_status;
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__be32 host_risc_reg[48];
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__be32 pcie_regs[4];
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__be32 host_reg[32];
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__be32 shadow_reg[11];
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__be32 risc_io_reg;
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__be16 mailbox_reg[32];
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__be32 xseq_gp_reg[256];
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__be32 xseq_0_reg[48];
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__be32 xseq_1_reg[16];
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__be32 xseq_2_reg[16];
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__be32 rseq_gp_reg[256];
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__be32 rseq_0_reg[32];
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__be32 rseq_1_reg[16];
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__be32 rseq_2_reg[16];
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__be32 rseq_3_reg[16];
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__be32 aseq_gp_reg[256];
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__be32 aseq_0_reg[32];
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__be32 aseq_1_reg[16];
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__be32 aseq_2_reg[16];
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__be32 aseq_3_reg[16];
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__be32 cmd_dma_reg[64];
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__be32 req0_dma_reg[15];
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__be32 resp0_dma_reg[15];
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__be32 req1_dma_reg[15];
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__be32 xmt0_dma_reg[32];
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__be32 xmt1_dma_reg[32];
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__be32 xmt2_dma_reg[32];
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__be32 xmt3_dma_reg[32];
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__be32 xmt4_dma_reg[32];
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__be32 xmt_data_dma_reg[16];
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__be32 rcvt0_data_dma_reg[32];
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__be32 rcvt1_data_dma_reg[32];
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__be32 risc_gp_reg[128];
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__be32 lmc_reg[128];
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__be32 fpm_hdw_reg[256];
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__be32 rq0_array_reg[256];
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__be32 rq1_array_reg[256];
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__be32 rp0_array_reg[256];
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__be32 rp1_array_reg[256];
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__be32 queue_control_reg[16];
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__be32 fb_hdw_reg[432];
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__be32 at0_array_reg[128];
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__be32 code_ram[0x2400];
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__be32 ext_mem[1];
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};
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#define EFT_NUM_BUFFERS 4
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#define EFT_BYTES_PER_BUFFER 0x4000
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#define EFT_SIZE ((EFT_BYTES_PER_BUFFER) * (EFT_NUM_BUFFERS))
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#define FCE_NUM_BUFFERS 64
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#define FCE_BYTES_PER_BUFFER 0x400
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#define FCE_SIZE ((FCE_BYTES_PER_BUFFER) * (FCE_NUM_BUFFERS))
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#define fce_calc_size(b) ((FCE_BYTES_PER_BUFFER) * (b))
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struct qla2xxx_fce_chain {
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__be32 type;
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__be32 chain_size;
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__be32 size;
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__be32 addr_l;
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__be32 addr_h;
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__be32 eregs[8];
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};
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/* used by exchange off load and extended login offload */
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struct qla2xxx_offld_chain {
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__be32 type;
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__be32 chain_size;
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__be32 size;
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__be32 reserved;
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__be64 addr;
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};
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struct qla2xxx_mq_chain {
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__be32 type;
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__be32 chain_size;
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__be32 count;
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__be32 qregs[4 * QLA_MQ_SIZE];
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};
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struct qla2xxx_mqueue_header {
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__be32 queue;
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#define TYPE_REQUEST_QUEUE 0x1
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#define TYPE_RESPONSE_QUEUE 0x2
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#define TYPE_ATIO_QUEUE 0x3
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__be32 number;
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__be32 size;
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};
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struct qla2xxx_mqueue_chain {
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__be32 type;
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__be32 chain_size;
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};
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#define DUMP_CHAIN_VARIANT 0x80000000
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#define DUMP_CHAIN_FCE 0x7FFFFAF0
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#define DUMP_CHAIN_MQ 0x7FFFFAF1
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#define DUMP_CHAIN_QUEUE 0x7FFFFAF2
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#define DUMP_CHAIN_EXLOGIN 0x7FFFFAF3
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#define DUMP_CHAIN_EXCHG 0x7FFFFAF4
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#define DUMP_CHAIN_LAST 0x80000000
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struct qla2xxx_fw_dump {
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uint8_t signature[4];
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__be32 version;
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__be32 fw_major_version;
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__be32 fw_minor_version;
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__be32 fw_subminor_version;
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__be32 fw_attributes;
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__be32 vendor;
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__be32 device;
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__be32 subsystem_vendor;
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__be32 subsystem_device;
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__be32 fixed_size;
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__be32 mem_size;
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__be32 req_q_size;
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__be32 rsp_q_size;
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__be32 eft_size;
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__be32 eft_addr_l;
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__be32 eft_addr_h;
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__be32 header_size;
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union {
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struct qla2100_fw_dump isp21;
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struct qla2300_fw_dump isp23;
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struct qla24xx_fw_dump isp24;
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struct qla25xx_fw_dump isp25;
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struct qla81xx_fw_dump isp81;
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struct qla83xx_fw_dump isp83;
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} isp;
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};
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#define QL_MSGHDR "qla2xxx"
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#define QL_DBG_DEFAULT1_MASK 0x1e400000
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#define ql_log_fatal 0 /* display fatal errors */
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#define ql_log_warn 1 /* display critical errors */
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#define ql_log_info 2 /* display all recovered errors */
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#define ql_log_all 3 /* This value is only used by ql_errlev.
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* No messages will use this value.
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* This should be always highest value
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* as compared to other log levels.
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*/
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extern uint ql_errlev;
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void __attribute__((format (printf, 4, 5)))
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ql_dbg(uint, scsi_qla_host_t *vha, uint, const char *fmt, ...);
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void __attribute__((format (printf, 4, 5)))
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ql_dbg_pci(uint, struct pci_dev *pdev, uint, const char *fmt, ...);
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void __attribute__((format (printf, 4, 5)))
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ql_dbg_qp(uint32_t, struct qla_qpair *, int32_t, const char *fmt, ...);
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void __attribute__((format (printf, 4, 5)))
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ql_log(uint, scsi_qla_host_t *vha, uint, const char *fmt, ...);
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void __attribute__((format (printf, 4, 5)))
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ql_log_pci(uint, struct pci_dev *pdev, uint, const char *fmt, ...);
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void __attribute__((format (printf, 4, 5)))
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ql_log_qp(uint32_t, struct qla_qpair *, int32_t, const char *fmt, ...);
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/* Debug Levels */
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/* The 0x40000000 is the max value any debug level can have
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* as ql2xextended_error_logging is of type signed int
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*/
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#define ql_dbg_init 0x40000000 /* Init Debug */
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#define ql_dbg_mbx 0x20000000 /* MBX Debug */
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#define ql_dbg_disc 0x10000000 /* Device Discovery Debug */
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#define ql_dbg_io 0x08000000 /* IO Tracing Debug */
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#define ql_dbg_dpc 0x04000000 /* DPC Thead Debug */
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#define ql_dbg_async 0x02000000 /* Async events Debug */
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#define ql_dbg_timer 0x01000000 /* Timer Debug */
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#define ql_dbg_user 0x00800000 /* User Space Interations Debug */
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#define ql_dbg_taskm 0x00400000 /* Task Management Debug */
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#define ql_dbg_aer 0x00200000 /* AER/EEH Debug */
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#define ql_dbg_multiq 0x00100000 /* MultiQ Debug */
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#define ql_dbg_p3p 0x00080000 /* P3P specific Debug */
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#define ql_dbg_vport 0x00040000 /* Virtual Port Debug */
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#define ql_dbg_buffer 0x00020000 /* For dumping the buffer/regs */
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#define ql_dbg_misc 0x00010000 /* For dumping everything that is not
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* not covered by upper categories
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*/
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#define ql_dbg_verbose 0x00008000 /* More verbosity for each level
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* This is to be used with other levels where
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* more verbosity is required. It might not
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* be applicable to all the levels.
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*/
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#define ql_dbg_tgt 0x00004000 /* Target mode */
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#define ql_dbg_tgt_mgt 0x00002000 /* Target mode management */
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#define ql_dbg_tgt_tmr 0x00001000 /* Target mode task management */
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#define ql_dbg_tgt_dif 0x00000800 /* Target mode dif */
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extern int qla27xx_dump_mpi_ram(struct qla_hw_data *, uint32_t, uint32_t *,
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uint32_t, void **);
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extern int qla24xx_dump_ram(struct qla_hw_data *, uint32_t, __be32 *,
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uint32_t, void **);
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extern void qla24xx_pause_risc(struct device_reg_24xx __iomem *,
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struct qla_hw_data *);
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extern int qla24xx_soft_reset(struct qla_hw_data *);
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static inline int
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ql_mask_match(uint level)
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{
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if (ql2xextended_error_logging == 1)
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ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK;
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return (level & ql2xextended_error_logging) == level;
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}
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