forked from Minki/linux
6127f4aee4
bo_va is being kfree'd twice, once in the call to amdgpu_vm_bo_rmv and then a short while later. Fix this double free by removing the 2nd kfree. Detected by CoverityScan, CID#1399524 ("Double Free") Reviewed-by: Monk Liu <monk.liu@amd.com> Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
222 lines
5.9 KiB
C
222 lines
5.9 KiB
C
/*
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* Copyright 2016 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "amdgpu.h"
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int amdgpu_allocate_static_csa(struct amdgpu_device *adev)
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{
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int r;
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void *ptr;
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r = amdgpu_bo_create_kernel(adev, AMDGPU_CSA_SIZE, PAGE_SIZE,
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AMDGPU_GEM_DOMAIN_VRAM, &adev->virt.csa_obj,
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&adev->virt.csa_vmid0_addr, &ptr);
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if (r)
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return r;
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memset(ptr, 0, AMDGPU_CSA_SIZE);
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return 0;
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}
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/*
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* amdgpu_map_static_csa should be called during amdgpu_vm_init
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* it maps virtual address "AMDGPU_VA_RESERVED_SIZE - AMDGPU_CSA_SIZE"
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* to this VM, and each command submission of GFX should use this virtual
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* address within META_DATA init package to support SRIOV gfx preemption.
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*/
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int amdgpu_map_static_csa(struct amdgpu_device *adev, struct amdgpu_vm *vm)
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{
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int r;
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struct amdgpu_bo_va *bo_va;
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struct ww_acquire_ctx ticket;
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struct list_head list;
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struct amdgpu_bo_list_entry pd;
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struct ttm_validate_buffer csa_tv;
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INIT_LIST_HEAD(&list);
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INIT_LIST_HEAD(&csa_tv.head);
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csa_tv.bo = &adev->virt.csa_obj->tbo;
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csa_tv.shared = true;
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list_add(&csa_tv.head, &list);
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amdgpu_vm_get_pd_bo(vm, &list, &pd);
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r = ttm_eu_reserve_buffers(&ticket, &list, true, NULL);
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if (r) {
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DRM_ERROR("failed to reserve CSA,PD BOs: err=%d\n", r);
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return r;
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}
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bo_va = amdgpu_vm_bo_add(adev, vm, adev->virt.csa_obj);
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if (!bo_va) {
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ttm_eu_backoff_reservation(&ticket, &list);
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DRM_ERROR("failed to create bo_va for static CSA\n");
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return -ENOMEM;
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}
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r = amdgpu_vm_bo_map(adev, bo_va, AMDGPU_CSA_VADDR, 0,AMDGPU_CSA_SIZE,
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AMDGPU_PTE_READABLE | AMDGPU_PTE_WRITEABLE |
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AMDGPU_PTE_EXECUTABLE);
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if (r) {
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DRM_ERROR("failed to do bo_map on static CSA, err=%d\n", r);
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amdgpu_vm_bo_rmv(adev, bo_va);
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ttm_eu_backoff_reservation(&ticket, &list);
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return r;
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}
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vm->csa_bo_va = bo_va;
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ttm_eu_backoff_reservation(&ticket, &list);
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return 0;
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}
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void amdgpu_virt_init_setting(struct amdgpu_device *adev)
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{
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/* enable virtual display */
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adev->mode_info.num_crtc = 1;
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adev->enable_virtual_display = true;
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mutex_init(&adev->virt.lock);
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}
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uint32_t amdgpu_virt_kiq_rreg(struct amdgpu_device *adev, uint32_t reg)
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{
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signed long r;
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uint32_t val;
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struct dma_fence *f;
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struct amdgpu_kiq *kiq = &adev->gfx.kiq;
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struct amdgpu_ring *ring = &kiq->ring;
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BUG_ON(!ring->funcs->emit_rreg);
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mutex_lock(&adev->virt.lock);
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amdgpu_ring_alloc(ring, 32);
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amdgpu_ring_emit_hdp_flush(ring);
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amdgpu_ring_emit_rreg(ring, reg);
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amdgpu_ring_emit_hdp_invalidate(ring);
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amdgpu_fence_emit(ring, &f);
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amdgpu_ring_commit(ring);
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mutex_unlock(&adev->virt.lock);
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r = dma_fence_wait(f, false);
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if (r)
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DRM_ERROR("wait for kiq fence error: %ld.\n", r);
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dma_fence_put(f);
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val = adev->wb.wb[adev->virt.reg_val_offs];
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return val;
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}
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void amdgpu_virt_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)
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{
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signed long r;
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struct dma_fence *f;
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struct amdgpu_kiq *kiq = &adev->gfx.kiq;
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struct amdgpu_ring *ring = &kiq->ring;
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BUG_ON(!ring->funcs->emit_wreg);
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mutex_lock(&adev->virt.lock);
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amdgpu_ring_alloc(ring, 32);
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amdgpu_ring_emit_hdp_flush(ring);
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amdgpu_ring_emit_wreg(ring, reg, v);
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amdgpu_ring_emit_hdp_invalidate(ring);
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amdgpu_fence_emit(ring, &f);
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amdgpu_ring_commit(ring);
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mutex_unlock(&adev->virt.lock);
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r = dma_fence_wait(f, false);
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if (r)
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DRM_ERROR("wait for kiq fence error: %ld.\n", r);
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dma_fence_put(f);
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}
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/**
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* amdgpu_virt_request_full_gpu() - request full gpu access
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* @amdgpu: amdgpu device.
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* @init: is driver init time.
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* When start to init/fini driver, first need to request full gpu access.
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* Return: Zero if request success, otherwise will return error.
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*/
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int amdgpu_virt_request_full_gpu(struct amdgpu_device *adev, bool init)
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{
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struct amdgpu_virt *virt = &adev->virt;
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int r;
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if (virt->ops && virt->ops->req_full_gpu) {
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r = virt->ops->req_full_gpu(adev, init);
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if (r)
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return r;
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adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME;
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}
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return 0;
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}
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/**
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* amdgpu_virt_release_full_gpu() - release full gpu access
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* @amdgpu: amdgpu device.
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* @init: is driver init time.
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* When finishing driver init/fini, need to release full gpu access.
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* Return: Zero if release success, otherwise will returen error.
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*/
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int amdgpu_virt_release_full_gpu(struct amdgpu_device *adev, bool init)
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{
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struct amdgpu_virt *virt = &adev->virt;
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int r;
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if (virt->ops && virt->ops->rel_full_gpu) {
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r = virt->ops->rel_full_gpu(adev, init);
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if (r)
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return r;
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adev->virt.caps |= AMDGPU_SRIOV_CAPS_RUNTIME;
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}
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return 0;
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}
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/**
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* amdgpu_virt_reset_gpu() - reset gpu
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* @amdgpu: amdgpu device.
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* Send reset command to GPU hypervisor to reset GPU that VM is using
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* Return: Zero if reset success, otherwise will return error.
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*/
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int amdgpu_virt_reset_gpu(struct amdgpu_device *adev)
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{
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struct amdgpu_virt *virt = &adev->virt;
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int r;
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if (virt->ops && virt->ops->reset_gpu) {
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r = virt->ops->reset_gpu(adev);
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if (r)
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return r;
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adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME;
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}
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return 0;
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}
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