forked from Minki/linux
1b2425e3c7
Make flush_data_cache_local, flush_instruction_cache_local and flush_tlb_all_local take a void * so they don't have to be cast when using on_each_cpu(). This becomes a problem when on_each_cpu is a macro (as it is in current -mm). Also move the prototype of flush_tlb_all_local into tlbflush.h and remove its declaration from .c files. Signed-off-by: Matthew Wilcox <willy@parisc-linux.org> Signed-off-by: Kyle McMartin <kyle@parisc-linux.org>
363 lines
9.6 KiB
C
363 lines
9.6 KiB
C
/* $Id: cache.c,v 1.4 2000/01/25 00:11:38 prumpf Exp $
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1999 Helge Deller (07-13-1999)
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* Copyright (C) 1999 SuSE GmbH Nuernberg
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* Copyright (C) 2000 Philipp Rumpf (prumpf@tux.org)
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*
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* Cache and TLB management
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*
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <linux/module.h>
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#include <linux/seq_file.h>
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#include <linux/pagemap.h>
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#include <asm/pdc.h>
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#include <asm/cache.h>
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#include <asm/cacheflush.h>
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#include <asm/tlbflush.h>
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#include <asm/system.h>
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#include <asm/page.h>
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#include <asm/pgalloc.h>
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#include <asm/processor.h>
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#include <asm/sections.h>
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int split_tlb __read_mostly;
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int dcache_stride __read_mostly;
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int icache_stride __read_mostly;
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EXPORT_SYMBOL(dcache_stride);
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#if defined(CONFIG_SMP)
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/* On some machines (e.g. ones with the Merced bus), there can be
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* only a single PxTLB broadcast at a time; this must be guaranteed
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* by software. We put a spinlock around all TLB flushes to
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* ensure this.
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*/
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DEFINE_SPINLOCK(pa_tlb_lock);
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EXPORT_SYMBOL(pa_tlb_lock);
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#endif
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struct pdc_cache_info cache_info __read_mostly;
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#ifndef CONFIG_PA20
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static struct pdc_btlb_info btlb_info __read_mostly;
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#endif
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#ifdef CONFIG_SMP
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void
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flush_data_cache(void)
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{
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on_each_cpu(flush_data_cache_local, NULL, 1, 1);
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}
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void
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flush_instruction_cache(void)
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{
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on_each_cpu(flush_instruction_cache_local, NULL, 1, 1);
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}
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#endif
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void
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flush_cache_all_local(void)
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{
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flush_instruction_cache_local(NULL);
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flush_data_cache_local(NULL);
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}
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EXPORT_SYMBOL(flush_cache_all_local);
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/* flushes EVERYTHING (tlb & cache) */
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void
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flush_all_caches(void)
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{
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flush_cache_all();
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flush_tlb_all();
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}
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EXPORT_SYMBOL(flush_all_caches);
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void
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update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte)
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{
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struct page *page = pte_page(pte);
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if (pfn_valid(page_to_pfn(page)) && page_mapping(page) &&
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test_bit(PG_dcache_dirty, &page->flags)) {
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flush_kernel_dcache_page(page_address(page));
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clear_bit(PG_dcache_dirty, &page->flags);
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}
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}
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void
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show_cache_info(struct seq_file *m)
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{
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seq_printf(m, "I-cache\t\t: %ld KB\n",
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cache_info.ic_size/1024 );
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seq_printf(m, "D-cache\t\t: %ld KB (%s%s, %d-way associative)\n",
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cache_info.dc_size/1024,
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(cache_info.dc_conf.cc_wt ? "WT":"WB"),
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(cache_info.dc_conf.cc_sh ? ", shared I/D":""),
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(cache_info.dc_conf.cc_assoc)
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);
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seq_printf(m, "ITLB entries\t: %ld\n" "DTLB entries\t: %ld%s\n",
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cache_info.it_size,
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cache_info.dt_size,
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cache_info.dt_conf.tc_sh ? " - shared with ITLB":""
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);
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#ifndef CONFIG_PA20
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/* BTLB - Block TLB */
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if (btlb_info.max_size==0) {
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seq_printf(m, "BTLB\t\t: not supported\n" );
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} else {
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seq_printf(m,
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"BTLB fixed\t: max. %d pages, pagesize=%d (%dMB)\n"
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"BTLB fix-entr.\t: %d instruction, %d data (%d combined)\n"
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"BTLB var-entr.\t: %d instruction, %d data (%d combined)\n",
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btlb_info.max_size, (int)4096,
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btlb_info.max_size>>8,
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btlb_info.fixed_range_info.num_i,
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btlb_info.fixed_range_info.num_d,
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btlb_info.fixed_range_info.num_comb,
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btlb_info.variable_range_info.num_i,
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btlb_info.variable_range_info.num_d,
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btlb_info.variable_range_info.num_comb
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);
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}
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#endif
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}
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void __init
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parisc_cache_init(void)
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{
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if (pdc_cache_info(&cache_info) < 0)
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panic("parisc_cache_init: pdc_cache_info failed");
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#if 0
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printk("ic_size %lx dc_size %lx it_size %lx\n",
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cache_info.ic_size,
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cache_info.dc_size,
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cache_info.it_size);
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printk("DC base 0x%lx stride 0x%lx count 0x%lx loop 0x%lx\n",
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cache_info.dc_base,
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cache_info.dc_stride,
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cache_info.dc_count,
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cache_info.dc_loop);
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printk("dc_conf = 0x%lx alias %d blk %d line %d shift %d\n",
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*(unsigned long *) (&cache_info.dc_conf),
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cache_info.dc_conf.cc_alias,
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cache_info.dc_conf.cc_block,
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cache_info.dc_conf.cc_line,
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cache_info.dc_conf.cc_shift);
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printk(" wt %d sh %d cst %d assoc %d\n",
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cache_info.dc_conf.cc_wt,
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cache_info.dc_conf.cc_sh,
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cache_info.dc_conf.cc_cst,
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cache_info.dc_conf.cc_assoc);
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printk("IC base 0x%lx stride 0x%lx count 0x%lx loop 0x%lx\n",
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cache_info.ic_base,
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cache_info.ic_stride,
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cache_info.ic_count,
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cache_info.ic_loop);
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printk("ic_conf = 0x%lx alias %d blk %d line %d shift %d\n",
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*(unsigned long *) (&cache_info.ic_conf),
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cache_info.ic_conf.cc_alias,
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cache_info.ic_conf.cc_block,
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cache_info.ic_conf.cc_line,
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cache_info.ic_conf.cc_shift);
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printk(" wt %d sh %d cst %d assoc %d\n",
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cache_info.ic_conf.cc_wt,
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cache_info.ic_conf.cc_sh,
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cache_info.ic_conf.cc_cst,
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cache_info.ic_conf.cc_assoc);
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printk("D-TLB conf: sh %d page %d cst %d aid %d pad1 %d \n",
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cache_info.dt_conf.tc_sh,
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cache_info.dt_conf.tc_page,
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cache_info.dt_conf.tc_cst,
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cache_info.dt_conf.tc_aid,
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cache_info.dt_conf.tc_pad1);
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printk("I-TLB conf: sh %d page %d cst %d aid %d pad1 %d \n",
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cache_info.it_conf.tc_sh,
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cache_info.it_conf.tc_page,
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cache_info.it_conf.tc_cst,
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cache_info.it_conf.tc_aid,
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cache_info.it_conf.tc_pad1);
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#endif
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split_tlb = 0;
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if (cache_info.dt_conf.tc_sh == 0 || cache_info.dt_conf.tc_sh == 2) {
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if (cache_info.dt_conf.tc_sh == 2)
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printk(KERN_WARNING "Unexpected TLB configuration. "
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"Will flush I/D separately (could be optimized).\n");
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split_tlb = 1;
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}
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/* "New and Improved" version from Jim Hull
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* (1 << (cc_block-1)) * (cc_line << (4 + cnf.cc_shift))
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* The following CAFL_STRIDE is an optimized version, see
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* http://lists.parisc-linux.org/pipermail/parisc-linux/2004-June/023625.html
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* http://lists.parisc-linux.org/pipermail/parisc-linux/2004-June/023671.html
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*/
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#define CAFL_STRIDE(cnf) (cnf.cc_line << (3 + cnf.cc_block + cnf.cc_shift))
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dcache_stride = CAFL_STRIDE(cache_info.dc_conf);
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icache_stride = CAFL_STRIDE(cache_info.ic_conf);
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#undef CAFL_STRIDE
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#ifndef CONFIG_PA20
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if (pdc_btlb_info(&btlb_info) < 0) {
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memset(&btlb_info, 0, sizeof btlb_info);
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}
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#endif
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if ((boot_cpu_data.pdc.capabilities & PDC_MODEL_NVA_MASK) ==
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PDC_MODEL_NVA_UNSUPPORTED) {
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printk(KERN_WARNING "parisc_cache_init: Only equivalent aliasing supported!\n");
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#if 0
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panic("SMP kernel required to avoid non-equivalent aliasing");
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#endif
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}
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}
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void disable_sr_hashing(void)
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{
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int srhash_type;
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switch (boot_cpu_data.cpu_type) {
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case pcx: /* We shouldn't get this far. setup.c should prevent it. */
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BUG();
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return;
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case pcxs:
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case pcxt:
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case pcxt_:
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srhash_type = SRHASH_PCXST;
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break;
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case pcxl:
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srhash_type = SRHASH_PCXL;
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break;
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case pcxl2: /* pcxl2 doesn't support space register hashing */
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return;
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default: /* Currently all PA2.0 machines use the same ins. sequence */
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srhash_type = SRHASH_PA20;
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break;
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}
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disable_sr_hashing_asm(srhash_type);
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}
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void flush_dcache_page(struct page *page)
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{
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struct address_space *mapping = page_mapping(page);
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struct vm_area_struct *mpnt;
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struct prio_tree_iter iter;
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unsigned long offset;
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unsigned long addr;
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pgoff_t pgoff;
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unsigned long pfn = page_to_pfn(page);
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if (mapping && !mapping_mapped(mapping)) {
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set_bit(PG_dcache_dirty, &page->flags);
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return;
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}
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flush_kernel_dcache_page(page_address(page));
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if (!mapping)
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return;
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pgoff = page->index << (PAGE_CACHE_SHIFT - PAGE_SHIFT);
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/* We have carefully arranged in arch_get_unmapped_area() that
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* *any* mappings of a file are always congruently mapped (whether
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* declared as MAP_PRIVATE or MAP_SHARED), so we only need
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* to flush one address here for them all to become coherent */
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flush_dcache_mmap_lock(mapping);
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vma_prio_tree_foreach(mpnt, &iter, &mapping->i_mmap, pgoff, pgoff) {
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offset = (pgoff - mpnt->vm_pgoff) << PAGE_SHIFT;
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addr = mpnt->vm_start + offset;
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/* Flush instructions produce non access tlb misses.
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* On PA, we nullify these instructions rather than
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* taking a page fault if the pte doesn't exist.
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* This is just for speed. If the page translation
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* isn't there, there's no point exciting the
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* nadtlb handler into a nullification frenzy.
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*
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* Make sure we really have this page: the private
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* mappings may cover this area but have COW'd this
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* particular page.
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*/
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if (translation_exists(mpnt, addr, pfn)) {
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__flush_cache_page(mpnt, addr);
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break;
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}
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}
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flush_dcache_mmap_unlock(mapping);
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}
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EXPORT_SYMBOL(flush_dcache_page);
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/* Defined in arch/parisc/kernel/pacache.S */
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EXPORT_SYMBOL(flush_kernel_dcache_range_asm);
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EXPORT_SYMBOL(flush_kernel_dcache_page);
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EXPORT_SYMBOL(flush_data_cache_local);
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EXPORT_SYMBOL(flush_kernel_icache_range_asm);
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void clear_user_page_asm(void *page, unsigned long vaddr)
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{
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/* This function is implemented in assembly in pacache.S */
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extern void __clear_user_page_asm(void *page, unsigned long vaddr);
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purge_tlb_start();
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__clear_user_page_asm(page, vaddr);
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purge_tlb_end();
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}
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#define FLUSH_THRESHOLD 0x80000 /* 0.5MB */
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int parisc_cache_flush_threshold __read_mostly = FLUSH_THRESHOLD;
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void parisc_setup_cache_timing(void)
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{
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unsigned long rangetime, alltime;
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unsigned long size;
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alltime = mfctl(16);
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flush_data_cache();
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alltime = mfctl(16) - alltime;
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size = (unsigned long)(_end - _text);
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rangetime = mfctl(16);
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flush_kernel_dcache_range((unsigned long)_text, size);
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rangetime = mfctl(16) - rangetime;
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printk(KERN_DEBUG "Whole cache flush %lu cycles, flushing %lu bytes %lu cycles\n",
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alltime, size, rangetime);
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/* Racy, but if we see an intermediate value, it's ok too... */
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parisc_cache_flush_threshold = size * alltime / rangetime;
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parisc_cache_flush_threshold = (parisc_cache_flush_threshold + L1_CACHE_BYTES - 1) &~ (L1_CACHE_BYTES - 1);
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if (!parisc_cache_flush_threshold)
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parisc_cache_flush_threshold = FLUSH_THRESHOLD;
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printk("Setting cache flush threshold to %x (%d CPUs online)\n", parisc_cache_flush_threshold, num_online_cpus());
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}
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