Archit Taneja 28e4309ab9 drm/msm/dsi: Populate PLL 10nm clock ops ... Populate PLL clock ops from downstream. This contains the VCO PLL ops and the registration of standard clk_divider and clk_mux clocks. Unlike 14nm PLL, the postdividers/mux of the slave PLL doesn't need to be set to the same values of the postdivs/mux of the master PLL. Hence, we don't need special postdivider clock ops like we did with the 14nm PLL driver. Like the previous PLL drivers, the implementation is slightly different from downstream. We don't use shadow clocks, but have the ability to reparent the RCGs to a different source. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>		2018-02-20 10:41:20 -05:00
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dsi_pll_10nm.c	drm/msm/dsi: Populate PLL 10nm clock ops	2018-02-20 10:41:20 -05:00
dsi_pll_14nm.c	clk: divider: fix incorrect usage of container_of	2017-12-28 15:16:04 -08:00
dsi_pll_28nm_8960.c	drm/msm: Set CLK_IGNORE_UNUSED flag for PLL clocks	2016-11-02 10:48:09 -04:00
dsi_pll_28nm.c	drm/msm: Set CLK_IGNORE_UNUSED flag for PLL clocks	2016-11-02 10:48:09 -04:00
dsi_pll.c	drm/msm/dsi: Add skeleton 10nm PHY/PLL code	2018-02-20 10:41:20 -05:00
dsi_pll.h	drm/msm/dsi: Add skeleton 10nm PHY/PLL code	2018-02-20 10:41:20 -05:00