forked from Minki/linux
2ea12442e3
drivers/built-in.o: In function `tc90522t_get_frontend': >> tc90522.c:(.text+0x260b64c): undefined reference to `__divdi3' >> tc90522.c:(.text+0x260b685): undefined reference to `__divdi3' >> tc90522.c:(.text+0x260b6bb): undefined reference to `__divdi3' >> tc90522.c:(.text+0x260b713): undefined reference to `__divdi3' drivers/built-in.o:tc90522.c:(.text+0x260bb64): more undefined references to `__divdi3' follow Reported-by: kbuild test robot <fengguang.wu@intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
841 lines
20 KiB
C
841 lines
20 KiB
C
/*
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* Toshiba TC90522 Demodulator
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*
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* Copyright (C) 2014 Akihiro Tsukada <tskd08@gmail.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/*
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* NOTICE:
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* This driver is incomplete and lacks init/config of the chips,
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* as the necessary info is not disclosed.
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* It assumes that users of this driver (such as a PCI bridge of
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* DTV receiver cards) properly init and configure the chip
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* via I2C *before* calling this driver's init() function.
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*
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* Currently, PT3 driver is the only one that uses this driver,
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* and contains init/config code in its firmware.
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* Thus some part of the code might be dependent on PT3 specific config.
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*/
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#include <linux/kernel.h>
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#include <linux/math64.h>
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#include <linux/dvb/frontend.h>
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#include "dvb_math.h"
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#include "tc90522.h"
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#define TC90522_I2C_THRU_REG 0xfe
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#define TC90522_MODULE_IDX(addr) (((u8)(addr) & 0x02U) >> 1)
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struct tc90522_state {
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struct tc90522_config cfg;
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struct dvb_frontend fe;
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struct i2c_client *i2c_client;
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struct i2c_adapter tuner_i2c;
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bool lna;
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};
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struct reg_val {
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u8 reg;
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u8 val;
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};
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static int
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reg_write(struct tc90522_state *state, const struct reg_val *regs, int num)
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{
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int i, ret;
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struct i2c_msg msg;
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ret = 0;
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msg.addr = state->i2c_client->addr;
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msg.flags = 0;
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msg.len = 2;
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for (i = 0; i < num; i++) {
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msg.buf = (u8 *)®s[i];
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ret = i2c_transfer(state->i2c_client->adapter, &msg, 1);
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if (ret == 0)
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ret = -EIO;
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if (ret < 0)
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return ret;
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}
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return 0;
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}
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static int reg_read(struct tc90522_state *state, u8 reg, u8 *val, u8 len)
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{
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struct i2c_msg msgs[2] = {
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{
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.addr = state->i2c_client->addr,
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.flags = 0,
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.buf = ®,
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.len = 1,
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},
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{
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.addr = state->i2c_client->addr,
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.flags = I2C_M_RD,
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.buf = val,
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.len = len,
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},
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};
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int ret;
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ret = i2c_transfer(state->i2c_client->adapter, msgs, ARRAY_SIZE(msgs));
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if (ret == ARRAY_SIZE(msgs))
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ret = 0;
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else if (ret >= 0)
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ret = -EIO;
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return ret;
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}
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static struct tc90522_state *cfg_to_state(struct tc90522_config *c)
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{
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return container_of(c, struct tc90522_state, cfg);
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}
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static int tc90522s_set_tsid(struct dvb_frontend *fe)
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{
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struct reg_val set_tsid[] = {
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{ 0x8f, 00 },
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{ 0x90, 00 }
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};
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set_tsid[0].val = (fe->dtv_property_cache.stream_id & 0xff00) >> 8;
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set_tsid[1].val = fe->dtv_property_cache.stream_id & 0xff;
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return reg_write(fe->demodulator_priv, set_tsid, ARRAY_SIZE(set_tsid));
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}
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static int tc90522t_set_layers(struct dvb_frontend *fe)
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{
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struct reg_val rv;
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u8 laysel;
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laysel = ~fe->dtv_property_cache.isdbt_layer_enabled & 0x07;
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laysel = (laysel & 0x01) << 2 | (laysel & 0x02) | (laysel & 0x04) >> 2;
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rv.reg = 0x71;
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rv.val = laysel;
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return reg_write(fe->demodulator_priv, &rv, 1);
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}
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/* frontend ops */
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static int tc90522s_read_status(struct dvb_frontend *fe, fe_status_t *status)
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{
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struct tc90522_state *state;
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int ret;
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u8 reg;
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state = fe->demodulator_priv;
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ret = reg_read(state, 0xc3, ®, 1);
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if (ret < 0)
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return ret;
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*status = 0;
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if (reg & 0x80) /* input level under min ? */
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return 0;
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*status |= FE_HAS_SIGNAL;
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if (reg & 0x60) /* carrier? */
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return 0;
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*status |= FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC;
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if (reg & 0x10)
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return 0;
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if (reg_read(state, 0xc5, ®, 1) < 0 || !(reg & 0x03))
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return 0;
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*status |= FE_HAS_LOCK;
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return 0;
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}
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static int tc90522t_read_status(struct dvb_frontend *fe, fe_status_t *status)
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{
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struct tc90522_state *state;
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int ret;
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u8 reg;
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state = fe->demodulator_priv;
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ret = reg_read(state, 0x96, ®, 1);
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if (ret < 0)
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return ret;
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*status = 0;
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if (reg & 0xe0) {
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*status = FE_HAS_SIGNAL | FE_HAS_CARRIER | FE_HAS_VITERBI
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| FE_HAS_SYNC | FE_HAS_LOCK;
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return 0;
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}
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ret = reg_read(state, 0x80, ®, 1);
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if (ret < 0)
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return ret;
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if (reg & 0xf0)
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return 0;
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*status |= FE_HAS_SIGNAL | FE_HAS_CARRIER;
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if (reg & 0x0c)
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return 0;
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*status |= FE_HAS_SYNC | FE_HAS_VITERBI;
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if (reg & 0x02)
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return 0;
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*status |= FE_HAS_LOCK;
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return 0;
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}
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static const fe_code_rate_t fec_conv_sat[] = {
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FEC_NONE, /* unused */
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FEC_1_2, /* for BPSK */
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FEC_1_2, FEC_2_3, FEC_3_4, FEC_5_6, FEC_7_8, /* for QPSK */
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FEC_2_3, /* for 8PSK. (trellis code) */
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};
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static int tc90522s_get_frontend(struct dvb_frontend *fe)
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{
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struct tc90522_state *state;
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struct dtv_frontend_properties *c;
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struct dtv_fe_stats *stats;
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int ret, i;
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int layers;
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u8 val[10];
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u32 cndat;
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state = fe->demodulator_priv;
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c = &fe->dtv_property_cache;
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c->delivery_system = SYS_ISDBS;
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layers = 0;
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ret = reg_read(state, 0xe8, val, 3);
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if (ret == 0) {
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int slots;
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u8 v;
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/* high/single layer */
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v = (val[0] & 0x70) >> 4;
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c->modulation = (v == 7) ? PSK_8 : QPSK;
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c->fec_inner = fec_conv_sat[v];
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c->layer[0].fec = c->fec_inner;
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c->layer[0].modulation = c->modulation;
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c->layer[0].segment_count = val[1] & 0x3f; /* slots */
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/* low layer */
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v = (val[0] & 0x07);
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c->layer[1].fec = fec_conv_sat[v];
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if (v == 0) /* no low layer */
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c->layer[1].segment_count = 0;
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else
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c->layer[1].segment_count = val[2] & 0x3f; /* slots */
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/* actually, BPSK if v==1, but not defined in fe_modulation_t */
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c->layer[1].modulation = QPSK;
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layers = (v > 0) ? 2 : 1;
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slots = c->layer[0].segment_count + c->layer[1].segment_count;
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c->symbol_rate = 28860000 * slots / 48;
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}
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/* statistics */
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stats = &c->strength;
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stats->len = 0;
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/* let the connected tuner set RSSI property cache */
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if (fe->ops.tuner_ops.get_rf_strength) {
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u16 dummy;
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fe->ops.tuner_ops.get_rf_strength(fe, &dummy);
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}
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stats = &c->cnr;
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stats->len = 1;
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stats->stat[0].scale = FE_SCALE_NOT_AVAILABLE;
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cndat = 0;
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ret = reg_read(state, 0xbc, val, 2);
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if (ret == 0)
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cndat = val[0] << 8 | val[1];
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if (cndat >= 3000) {
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u32 p, p4;
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s64 cn;
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cndat -= 3000; /* cndat: 4.12 fixed point float */
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/*
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* cnr[mdB] = -1634.6 * P^5 + 14341 * P^4 - 50259 * P^3
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* + 88977 * P^2 - 89565 * P + 58857
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* (P = sqrt(cndat) / 64)
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*/
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/* p := sqrt(cndat) << 8 = P << 14, 2.14 fixed point float */
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/* cn = cnr << 3 */
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p = int_sqrt(cndat << 16);
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p4 = cndat * cndat;
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cn = div64_s64(-16346LL * p4 * p, 10) >> 35;
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cn += (14341LL * p4) >> 21;
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cn -= (50259LL * cndat * p) >> 23;
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cn += (88977LL * cndat) >> 9;
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cn -= (89565LL * p) >> 11;
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cn += 58857 << 3;
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stats->stat[0].svalue = cn >> 3;
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stats->stat[0].scale = FE_SCALE_DECIBEL;
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}
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/* per-layer post viterbi BER (or PER? config dependent?) */
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stats = &c->post_bit_error;
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memset(stats, 0, sizeof(*stats));
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stats->len = layers;
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ret = reg_read(state, 0xeb, val, 10);
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if (ret < 0)
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for (i = 0; i < layers; i++)
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stats->stat[i].scale = FE_SCALE_NOT_AVAILABLE;
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else {
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for (i = 0; i < layers; i++) {
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stats->stat[i].scale = FE_SCALE_COUNTER;
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stats->stat[i].uvalue = val[i * 5] << 16
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| val[i * 5 + 1] << 8 | val[i * 5 + 2];
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}
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}
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stats = &c->post_bit_count;
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memset(stats, 0, sizeof(*stats));
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stats->len = layers;
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if (ret < 0)
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for (i = 0; i < layers; i++)
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stats->stat[i].scale = FE_SCALE_NOT_AVAILABLE;
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else {
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for (i = 0; i < layers; i++) {
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stats->stat[i].scale = FE_SCALE_COUNTER;
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stats->stat[i].uvalue =
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val[i * 5 + 3] << 8 | val[i * 5 + 4];
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stats->stat[i].uvalue *= 204 * 8;
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}
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}
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return 0;
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}
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static const fe_transmit_mode_t tm_conv[] = {
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TRANSMISSION_MODE_2K,
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TRANSMISSION_MODE_4K,
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TRANSMISSION_MODE_8K,
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0
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};
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static const fe_code_rate_t fec_conv_ter[] = {
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FEC_1_2, FEC_2_3, FEC_3_4, FEC_5_6, FEC_7_8, 0, 0, 0
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};
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static const fe_modulation_t mod_conv[] = {
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DQPSK, QPSK, QAM_16, QAM_64, 0, 0, 0, 0
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};
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static int tc90522t_get_frontend(struct dvb_frontend *fe)
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{
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struct tc90522_state *state;
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struct dtv_frontend_properties *c;
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struct dtv_fe_stats *stats;
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int ret, i;
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int layers;
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u8 val[15], mode;
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u32 cndat;
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state = fe->demodulator_priv;
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c = &fe->dtv_property_cache;
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c->delivery_system = SYS_ISDBT;
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c->bandwidth_hz = 6000000;
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mode = 1;
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ret = reg_read(state, 0xb0, val, 1);
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if (ret == 0) {
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mode = (val[0] & 0xc0) >> 2;
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c->transmission_mode = tm_conv[mode];
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c->guard_interval = (val[0] & 0x30) >> 4;
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}
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ret = reg_read(state, 0xb2, val, 6);
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layers = 0;
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if (ret == 0) {
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u8 v;
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c->isdbt_partial_reception = val[0] & 0x01;
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c->isdbt_sb_mode = (val[0] & 0xc0) == 0x01;
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/* layer A */
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v = (val[2] & 0x78) >> 3;
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if (v == 0x0f)
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c->layer[0].segment_count = 0;
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else {
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layers++;
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c->layer[0].segment_count = v;
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c->layer[0].fec = fec_conv_ter[(val[1] & 0x1c) >> 2];
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c->layer[0].modulation = mod_conv[(val[1] & 0xe0) >> 5];
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v = (val[1] & 0x03) << 1 | (val[2] & 0x80) >> 7;
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c->layer[0].interleaving = v;
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}
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/* layer B */
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v = (val[3] & 0x03) << 1 | (val[4] & 0xc0) >> 6;
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if (v == 0x0f)
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c->layer[1].segment_count = 0;
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else {
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layers++;
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c->layer[1].segment_count = v;
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c->layer[1].fec = fec_conv_ter[(val[3] & 0xe0) >> 5];
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c->layer[1].modulation = mod_conv[(val[2] & 0x07)];
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c->layer[1].interleaving = (val[3] & 0x1c) >> 2;
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}
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/* layer C */
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v = (val[5] & 0x1e) >> 1;
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if (v == 0x0f)
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c->layer[2].segment_count = 0;
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else {
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layers++;
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c->layer[2].segment_count = v;
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c->layer[2].fec = fec_conv_ter[(val[4] & 0x07)];
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c->layer[2].modulation = mod_conv[(val[4] & 0x38) >> 3];
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c->layer[2].interleaving = (val[5] & 0xe0) >> 5;
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}
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}
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/* statistics */
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stats = &c->strength;
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stats->len = 0;
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/* let the connected tuner set RSSI property cache */
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if (fe->ops.tuner_ops.get_rf_strength) {
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u16 dummy;
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fe->ops.tuner_ops.get_rf_strength(fe, &dummy);
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}
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stats = &c->cnr;
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stats->len = 1;
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stats->stat[0].scale = FE_SCALE_NOT_AVAILABLE;
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cndat = 0;
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ret = reg_read(state, 0x8b, val, 3);
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if (ret == 0)
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cndat = val[0] << 16 | val[1] << 8 | val[2];
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if (cndat != 0) {
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u32 p, tmp;
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s64 cn;
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/*
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* cnr[mdB] = 0.024 P^4 - 1.6 P^3 + 39.8 P^2 + 549.1 P + 3096.5
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* (P = 10log10(5505024/cndat))
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*/
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/* cn = cnr << 3 (61.3 fixed point float */
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/* p = 10log10(5505024/cndat) << 24 (8.24 fixed point float)*/
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p = intlog10(5505024) - intlog10(cndat);
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p *= 10;
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cn = 24772;
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cn += div64_s64(43827LL * p, 10) >> 24;
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tmp = p >> 8;
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cn += div64_s64(3184LL * tmp * tmp, 10) >> 32;
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tmp = p >> 13;
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cn -= div64_s64(128LL * tmp * tmp * tmp, 10) >> 33;
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tmp = p >> 18;
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cn += div64_s64(192LL * tmp * tmp * tmp * tmp, 1000) >> 24;
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stats->stat[0].svalue = cn >> 3;
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stats->stat[0].scale = FE_SCALE_DECIBEL;
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}
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/* per-layer post viterbi BER (or PER? config dependent?) */
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stats = &c->post_bit_error;
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memset(stats, 0, sizeof(*stats));
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stats->len = layers;
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ret = reg_read(state, 0x9d, val, 15);
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if (ret < 0)
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for (i = 0; i < layers; i++)
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stats->stat[i].scale = FE_SCALE_NOT_AVAILABLE;
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else {
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for (i = 0; i < layers; i++) {
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stats->stat[i].scale = FE_SCALE_COUNTER;
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stats->stat[i].uvalue = val[i * 3] << 16
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| val[i * 3 + 1] << 8 | val[i * 3 + 2];
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}
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}
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stats = &c->post_bit_count;
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memset(stats, 0, sizeof(*stats));
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stats->len = layers;
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if (ret < 0)
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for (i = 0; i < layers; i++)
|
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stats->stat[i].scale = FE_SCALE_NOT_AVAILABLE;
|
|
else {
|
|
for (i = 0; i < layers; i++) {
|
|
stats->stat[i].scale = FE_SCALE_COUNTER;
|
|
stats->stat[i].uvalue =
|
|
val[9 + i * 2] << 8 | val[9 + i * 2 + 1];
|
|
stats->stat[i].uvalue *= 204 * 8;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct reg_val reset_sat = { 0x03, 0x01 };
|
|
static const struct reg_val reset_ter = { 0x01, 0x40 };
|
|
|
|
static int tc90522_set_frontend(struct dvb_frontend *fe)
|
|
{
|
|
struct tc90522_state *state;
|
|
int ret;
|
|
|
|
state = fe->demodulator_priv;
|
|
|
|
if (fe->ops.tuner_ops.set_params)
|
|
ret = fe->ops.tuner_ops.set_params(fe);
|
|
else
|
|
ret = -ENODEV;
|
|
if (ret < 0)
|
|
goto failed;
|
|
|
|
if (fe->ops.delsys[0] == SYS_ISDBS) {
|
|
ret = tc90522s_set_tsid(fe);
|
|
if (ret < 0)
|
|
goto failed;
|
|
ret = reg_write(state, &reset_sat, 1);
|
|
} else {
|
|
ret = tc90522t_set_layers(fe);
|
|
if (ret < 0)
|
|
goto failed;
|
|
ret = reg_write(state, &reset_ter, 1);
|
|
}
|
|
if (ret < 0)
|
|
goto failed;
|
|
|
|
return 0;
|
|
|
|
failed:
|
|
dev_warn(&state->tuner_i2c.dev, "(%s) failed. [adap%d-fe%d]\n",
|
|
__func__, fe->dvb->num, fe->id);
|
|
return ret;
|
|
}
|
|
|
|
static int tc90522_get_tune_settings(struct dvb_frontend *fe,
|
|
struct dvb_frontend_tune_settings *settings)
|
|
{
|
|
if (fe->ops.delsys[0] == SYS_ISDBS) {
|
|
settings->min_delay_ms = 250;
|
|
settings->step_size = 1000;
|
|
settings->max_drift = settings->step_size * 2;
|
|
} else {
|
|
settings->min_delay_ms = 400;
|
|
settings->step_size = 142857;
|
|
settings->max_drift = settings->step_size;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static int tc90522_set_if_agc(struct dvb_frontend *fe, bool on)
|
|
{
|
|
struct reg_val agc_sat[] = {
|
|
{ 0x0a, 0x00 },
|
|
{ 0x10, 0x30 },
|
|
{ 0x11, 0x00 },
|
|
{ 0x03, 0x01 },
|
|
};
|
|
struct reg_val agc_ter[] = {
|
|
{ 0x25, 0x00 },
|
|
{ 0x23, 0x4c },
|
|
{ 0x01, 0x40 },
|
|
};
|
|
struct tc90522_state *state;
|
|
struct reg_val *rv;
|
|
int num;
|
|
|
|
state = fe->demodulator_priv;
|
|
if (fe->ops.delsys[0] == SYS_ISDBS) {
|
|
agc_sat[0].val = on ? 0xff : 0x00;
|
|
agc_sat[1].val |= 0x80;
|
|
agc_sat[1].val |= on ? 0x01 : 0x00;
|
|
agc_sat[2].val |= on ? 0x40 : 0x00;
|
|
rv = agc_sat;
|
|
num = ARRAY_SIZE(agc_sat);
|
|
} else {
|
|
agc_ter[0].val = on ? 0x40 : 0x00;
|
|
agc_ter[1].val |= on ? 0x00 : 0x01;
|
|
rv = agc_ter;
|
|
num = ARRAY_SIZE(agc_ter);
|
|
}
|
|
return reg_write(state, rv, num);
|
|
}
|
|
|
|
static const struct reg_val sleep_sat = { 0x17, 0x01 };
|
|
static const struct reg_val sleep_ter = { 0x03, 0x90 };
|
|
|
|
static int tc90522_sleep(struct dvb_frontend *fe)
|
|
{
|
|
struct tc90522_state *state;
|
|
int ret;
|
|
|
|
state = fe->demodulator_priv;
|
|
if (fe->ops.delsys[0] == SYS_ISDBS)
|
|
ret = reg_write(state, &sleep_sat, 1);
|
|
else {
|
|
ret = reg_write(state, &sleep_ter, 1);
|
|
if (ret == 0 && fe->ops.set_lna &&
|
|
fe->dtv_property_cache.lna == LNA_AUTO) {
|
|
fe->dtv_property_cache.lna = 0;
|
|
ret = fe->ops.set_lna(fe);
|
|
fe->dtv_property_cache.lna = LNA_AUTO;
|
|
}
|
|
}
|
|
if (ret < 0)
|
|
dev_warn(&state->tuner_i2c.dev,
|
|
"(%s) failed. [adap%d-fe%d]\n",
|
|
__func__, fe->dvb->num, fe->id);
|
|
return ret;
|
|
}
|
|
|
|
static const struct reg_val wakeup_sat = { 0x17, 0x00 };
|
|
static const struct reg_val wakeup_ter = { 0x03, 0x80 };
|
|
|
|
static int tc90522_init(struct dvb_frontend *fe)
|
|
{
|
|
struct tc90522_state *state;
|
|
int ret;
|
|
|
|
/*
|
|
* Because the init sequence is not public,
|
|
* the parent device/driver should have init'ed the device before.
|
|
* just wake up the device here.
|
|
*/
|
|
|
|
state = fe->demodulator_priv;
|
|
if (fe->ops.delsys[0] == SYS_ISDBS)
|
|
ret = reg_write(state, &wakeup_sat, 1);
|
|
else {
|
|
ret = reg_write(state, &wakeup_ter, 1);
|
|
if (ret == 0 && fe->ops.set_lna &&
|
|
fe->dtv_property_cache.lna == LNA_AUTO) {
|
|
fe->dtv_property_cache.lna = 1;
|
|
ret = fe->ops.set_lna(fe);
|
|
fe->dtv_property_cache.lna = LNA_AUTO;
|
|
}
|
|
}
|
|
if (ret < 0) {
|
|
dev_warn(&state->tuner_i2c.dev,
|
|
"(%s) failed. [adap%d-fe%d]\n",
|
|
__func__, fe->dvb->num, fe->id);
|
|
return ret;
|
|
}
|
|
|
|
/* prefer 'all-layers' to 'none' as a default */
|
|
if (fe->dtv_property_cache.isdbt_layer_enabled == 0)
|
|
fe->dtv_property_cache.isdbt_layer_enabled = 7;
|
|
return tc90522_set_if_agc(fe, true);
|
|
}
|
|
|
|
|
|
/*
|
|
* tuner I2C adapter functions
|
|
*/
|
|
|
|
static int
|
|
tc90522_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
|
|
{
|
|
struct tc90522_state *state;
|
|
struct i2c_msg *new_msgs;
|
|
int i, j;
|
|
int ret, rd_num;
|
|
u8 wbuf[256];
|
|
u8 *p, *bufend;
|
|
|
|
if (num <= 0)
|
|
return -EINVAL;
|
|
|
|
rd_num = 0;
|
|
for (i = 0; i < num; i++)
|
|
if (msgs[i].flags & I2C_M_RD)
|
|
rd_num++;
|
|
new_msgs = kmalloc(sizeof(*new_msgs) * (num + rd_num), GFP_KERNEL);
|
|
if (!new_msgs)
|
|
return -ENOMEM;
|
|
|
|
state = i2c_get_adapdata(adap);
|
|
p = wbuf;
|
|
bufend = wbuf + sizeof(wbuf);
|
|
for (i = 0, j = 0; i < num; i++, j++) {
|
|
new_msgs[j].addr = state->i2c_client->addr;
|
|
new_msgs[j].flags = msgs[i].flags;
|
|
|
|
if (msgs[i].flags & I2C_M_RD) {
|
|
new_msgs[j].flags &= ~I2C_M_RD;
|
|
if (p + 2 > bufend)
|
|
break;
|
|
p[0] = TC90522_I2C_THRU_REG;
|
|
p[1] = msgs[i].addr << 1 | 0x01;
|
|
new_msgs[j].buf = p;
|
|
new_msgs[j].len = 2;
|
|
p += 2;
|
|
j++;
|
|
new_msgs[j].addr = state->i2c_client->addr;
|
|
new_msgs[j].flags = msgs[i].flags;
|
|
new_msgs[j].buf = msgs[i].buf;
|
|
new_msgs[j].len = msgs[i].len;
|
|
continue;
|
|
}
|
|
|
|
if (p + msgs[i].len + 2 > bufend)
|
|
break;
|
|
p[0] = TC90522_I2C_THRU_REG;
|
|
p[1] = msgs[i].addr << 1;
|
|
memcpy(p + 2, msgs[i].buf, msgs[i].len);
|
|
new_msgs[j].buf = p;
|
|
new_msgs[j].len = msgs[i].len + 2;
|
|
p += new_msgs[j].len;
|
|
}
|
|
|
|
if (i < num)
|
|
ret = -ENOMEM;
|
|
else
|
|
ret = i2c_transfer(state->i2c_client->adapter, new_msgs, j);
|
|
if (ret >= 0 && ret < j)
|
|
ret = -EIO;
|
|
kfree(new_msgs);
|
|
return (ret == j) ? num : ret;
|
|
}
|
|
|
|
static u32 tc90522_functionality(struct i2c_adapter *adap)
|
|
{
|
|
return I2C_FUNC_I2C;
|
|
}
|
|
|
|
static const struct i2c_algorithm tc90522_tuner_i2c_algo = {
|
|
.master_xfer = &tc90522_master_xfer,
|
|
.functionality = &tc90522_functionality,
|
|
};
|
|
|
|
|
|
/*
|
|
* I2C driver functions
|
|
*/
|
|
|
|
static const struct dvb_frontend_ops tc90522_ops_sat = {
|
|
.delsys = { SYS_ISDBS },
|
|
.info = {
|
|
.name = "Toshiba TC90522 ISDB-S module",
|
|
.frequency_min = 950000,
|
|
.frequency_max = 2150000,
|
|
.caps = FE_CAN_INVERSION_AUTO | FE_CAN_FEC_AUTO |
|
|
FE_CAN_QAM_AUTO | FE_CAN_TRANSMISSION_MODE_AUTO |
|
|
FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_HIERARCHY_AUTO,
|
|
},
|
|
|
|
.init = tc90522_init,
|
|
.sleep = tc90522_sleep,
|
|
.set_frontend = tc90522_set_frontend,
|
|
.get_tune_settings = tc90522_get_tune_settings,
|
|
|
|
.get_frontend = tc90522s_get_frontend,
|
|
.read_status = tc90522s_read_status,
|
|
};
|
|
|
|
static const struct dvb_frontend_ops tc90522_ops_ter = {
|
|
.delsys = { SYS_ISDBT },
|
|
.info = {
|
|
.name = "Toshiba TC90522 ISDB-T module",
|
|
.frequency_min = 470000000,
|
|
.frequency_max = 770000000,
|
|
.frequency_stepsize = 142857,
|
|
.caps = FE_CAN_INVERSION_AUTO |
|
|
FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
|
|
FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
|
|
FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 |
|
|
FE_CAN_QAM_AUTO | FE_CAN_TRANSMISSION_MODE_AUTO |
|
|
FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_RECOVER |
|
|
FE_CAN_HIERARCHY_AUTO,
|
|
},
|
|
|
|
.init = tc90522_init,
|
|
.sleep = tc90522_sleep,
|
|
.set_frontend = tc90522_set_frontend,
|
|
.get_tune_settings = tc90522_get_tune_settings,
|
|
|
|
.get_frontend = tc90522t_get_frontend,
|
|
.read_status = tc90522t_read_status,
|
|
};
|
|
|
|
|
|
static int tc90522_probe(struct i2c_client *client,
|
|
const struct i2c_device_id *id)
|
|
{
|
|
struct tc90522_state *state;
|
|
struct tc90522_config *cfg;
|
|
const struct dvb_frontend_ops *ops;
|
|
struct i2c_adapter *adap;
|
|
int ret;
|
|
|
|
state = kzalloc(sizeof(*state), GFP_KERNEL);
|
|
if (!state)
|
|
return -ENOMEM;
|
|
state->i2c_client = client;
|
|
|
|
cfg = client->dev.platform_data;
|
|
memcpy(&state->cfg, cfg, sizeof(state->cfg));
|
|
cfg->fe = state->cfg.fe = &state->fe;
|
|
ops = id->driver_data == 0 ? &tc90522_ops_sat : &tc90522_ops_ter;
|
|
memcpy(&state->fe.ops, ops, sizeof(*ops));
|
|
state->fe.demodulator_priv = state;
|
|
|
|
adap = &state->tuner_i2c;
|
|
adap->owner = THIS_MODULE;
|
|
adap->algo = &tc90522_tuner_i2c_algo;
|
|
adap->dev.parent = &client->dev;
|
|
strlcpy(adap->name, "tc90522_sub", sizeof(adap->name));
|
|
i2c_set_adapdata(adap, state);
|
|
ret = i2c_add_adapter(adap);
|
|
if (ret < 0)
|
|
goto err;
|
|
cfg->tuner_i2c = state->cfg.tuner_i2c = adap;
|
|
|
|
i2c_set_clientdata(client, &state->cfg);
|
|
dev_info(&client->dev, "Toshiba TC90522 attached.\n");
|
|
return 0;
|
|
|
|
err:
|
|
kfree(state);
|
|
return ret;
|
|
}
|
|
|
|
static int tc90522_remove(struct i2c_client *client)
|
|
{
|
|
struct tc90522_state *state;
|
|
|
|
state = cfg_to_state(i2c_get_clientdata(client));
|
|
i2c_del_adapter(&state->tuner_i2c);
|
|
kfree(state);
|
|
return 0;
|
|
}
|
|
|
|
|
|
static const struct i2c_device_id tc90522_id[] = {
|
|
{ TC90522_I2C_DEV_SAT, 0 },
|
|
{ TC90522_I2C_DEV_TER, 1 },
|
|
{}
|
|
};
|
|
MODULE_DEVICE_TABLE(i2c, tc90522_id);
|
|
|
|
static struct i2c_driver tc90522_driver = {
|
|
.driver = {
|
|
.name = "tc90522",
|
|
},
|
|
.probe = tc90522_probe,
|
|
.remove = tc90522_remove,
|
|
.id_table = tc90522_id,
|
|
};
|
|
|
|
module_i2c_driver(tc90522_driver);
|
|
|
|
MODULE_DESCRIPTION("Toshiba TC90522 frontend");
|
|
MODULE_AUTHOR("Akihiro TSUKADA");
|
|
MODULE_LICENSE("GPL");
|