forked from Minki/linux
bcb63314e2
Drop the FSF's postal address from the source code files that typically contain mostly the license text. Of the 628 removed instances, 578 are outdated. The patch has been created with the following command without manual edits: git grep -l "675 Mass Ave\|59 Temple Place\|51 Franklin St" -- \ drivers/media/ include/media|while read i; do i=$i perl -e ' open(F,"< $ENV{i}"); $a=join("", <F>); $a =~ s/[ \t]*\*\n.*You should.*\n.*along with.*\n.*(\n.*USA.*$)?\n//m && $a =~ s/(^.*)Or, (point your browser to) /$1To obtain the license, $2\n$1/m; close(F); open(F, "> $ENV{i}"); print F $a; close(F);'; done Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
775 lines
20 KiB
C
775 lines
20 KiB
C
/*
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* Linux-DVB Driver for DiBcom's DiB0070 base-band RF Tuner.
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*
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* Copyright (C) 2005-9 DiBcom (http://www.dibcom.fr/)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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*
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* GNU General Public License for more details.
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*
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*
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* This code is more or less generated from another driver, please
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* excuse some codingstyle oddities.
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*
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/kernel.h>
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#include <linux/slab.h>
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#include <linux/i2c.h>
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#include <linux/mutex.h>
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#include "dvb_frontend.h"
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#include "dib0070.h"
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#include "dibx000_common.h"
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static int debug;
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module_param(debug, int, 0644);
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MODULE_PARM_DESC(debug, "turn on debugging (default: 0)");
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#define dprintk(fmt, arg...) do { \
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if (debug) \
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printk(KERN_DEBUG pr_fmt("%s: " fmt), \
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__func__, ##arg); \
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} while (0)
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#define DIB0070_P1D 0x00
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#define DIB0070_P1F 0x01
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#define DIB0070_P1G 0x03
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#define DIB0070S_P1A 0x02
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struct dib0070_state {
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struct i2c_adapter *i2c;
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struct dvb_frontend *fe;
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const struct dib0070_config *cfg;
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u16 wbd_ff_offset;
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u8 revision;
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enum frontend_tune_state tune_state;
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u32 current_rf;
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/* for the captrim binary search */
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s8 step;
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u16 adc_diff;
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s8 captrim;
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s8 fcaptrim;
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u16 lo4;
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const struct dib0070_tuning *current_tune_table_index;
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const struct dib0070_lna_match *lna_match;
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u8 wbd_gain_current;
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u16 wbd_offset_3_3[2];
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/* for the I2C transfer */
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struct i2c_msg msg[2];
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u8 i2c_write_buffer[3];
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u8 i2c_read_buffer[2];
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struct mutex i2c_buffer_lock;
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};
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static u16 dib0070_read_reg(struct dib0070_state *state, u8 reg)
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{
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u16 ret;
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if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) {
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dprintk("could not acquire lock\n");
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return 0;
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}
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state->i2c_write_buffer[0] = reg;
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memset(state->msg, 0, 2 * sizeof(struct i2c_msg));
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state->msg[0].addr = state->cfg->i2c_address;
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state->msg[0].flags = 0;
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state->msg[0].buf = state->i2c_write_buffer;
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state->msg[0].len = 1;
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state->msg[1].addr = state->cfg->i2c_address;
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state->msg[1].flags = I2C_M_RD;
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state->msg[1].buf = state->i2c_read_buffer;
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state->msg[1].len = 2;
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if (i2c_transfer(state->i2c, state->msg, 2) != 2) {
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pr_warn("DiB0070 I2C read failed\n");
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ret = 0;
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} else
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ret = (state->i2c_read_buffer[0] << 8)
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| state->i2c_read_buffer[1];
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mutex_unlock(&state->i2c_buffer_lock);
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return ret;
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}
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static int dib0070_write_reg(struct dib0070_state *state, u8 reg, u16 val)
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{
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int ret;
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if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) {
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dprintk("could not acquire lock\n");
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return -EINVAL;
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}
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state->i2c_write_buffer[0] = reg;
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state->i2c_write_buffer[1] = val >> 8;
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state->i2c_write_buffer[2] = val & 0xff;
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memset(state->msg, 0, sizeof(struct i2c_msg));
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state->msg[0].addr = state->cfg->i2c_address;
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state->msg[0].flags = 0;
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state->msg[0].buf = state->i2c_write_buffer;
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state->msg[0].len = 3;
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if (i2c_transfer(state->i2c, state->msg, 1) != 1) {
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pr_warn("DiB0070 I2C write failed\n");
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ret = -EREMOTEIO;
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} else
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ret = 0;
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mutex_unlock(&state->i2c_buffer_lock);
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return ret;
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}
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#define HARD_RESET(state) do { \
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state->cfg->sleep(state->fe, 0); \
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if (state->cfg->reset) { \
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state->cfg->reset(state->fe,1); msleep(10); \
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state->cfg->reset(state->fe,0); msleep(10); \
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} \
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} while (0)
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static int dib0070_set_bandwidth(struct dvb_frontend *fe)
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{
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struct dib0070_state *state = fe->tuner_priv;
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u16 tmp = dib0070_read_reg(state, 0x02) & 0x3fff;
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if (state->fe->dtv_property_cache.bandwidth_hz/1000 > 7000)
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tmp |= (0 << 14);
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else if (state->fe->dtv_property_cache.bandwidth_hz/1000 > 6000)
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tmp |= (1 << 14);
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else if (state->fe->dtv_property_cache.bandwidth_hz/1000 > 5000)
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tmp |= (2 << 14);
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else
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tmp |= (3 << 14);
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dib0070_write_reg(state, 0x02, tmp);
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/* sharpen the BB filter in ISDB-T to have higher immunity to adjacent channels */
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if (state->fe->dtv_property_cache.delivery_system == SYS_ISDBT) {
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u16 value = dib0070_read_reg(state, 0x17);
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dib0070_write_reg(state, 0x17, value & 0xfffc);
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tmp = dib0070_read_reg(state, 0x01) & 0x01ff;
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dib0070_write_reg(state, 0x01, tmp | (60 << 9));
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dib0070_write_reg(state, 0x17, value);
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}
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return 0;
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}
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static int dib0070_captrim(struct dib0070_state *state, enum frontend_tune_state *tune_state)
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{
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int8_t step_sign;
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u16 adc;
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int ret = 0;
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if (*tune_state == CT_TUNER_STEP_0) {
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dib0070_write_reg(state, 0x0f, 0xed10);
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dib0070_write_reg(state, 0x17, 0x0034);
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dib0070_write_reg(state, 0x18, 0x0032);
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state->step = state->captrim = state->fcaptrim = 64;
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state->adc_diff = 3000;
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ret = 20;
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*tune_state = CT_TUNER_STEP_1;
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} else if (*tune_state == CT_TUNER_STEP_1) {
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state->step /= 2;
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dib0070_write_reg(state, 0x14, state->lo4 | state->captrim);
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ret = 15;
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*tune_state = CT_TUNER_STEP_2;
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} else if (*tune_state == CT_TUNER_STEP_2) {
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adc = dib0070_read_reg(state, 0x19);
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dprintk("CAPTRIM=%hd; ADC = %hd (ADC) & %dmV\n", state->captrim, adc, (u32) adc*(u32)1800/(u32)1024);
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if (adc >= 400) {
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adc -= 400;
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step_sign = -1;
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} else {
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adc = 400 - adc;
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step_sign = 1;
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}
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if (adc < state->adc_diff) {
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dprintk("CAPTRIM=%hd is closer to target (%hd/%hd)\n", state->captrim, adc, state->adc_diff);
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state->adc_diff = adc;
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state->fcaptrim = state->captrim;
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}
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state->captrim += (step_sign * state->step);
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if (state->step >= 1)
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*tune_state = CT_TUNER_STEP_1;
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else
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*tune_state = CT_TUNER_STEP_3;
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} else if (*tune_state == CT_TUNER_STEP_3) {
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dib0070_write_reg(state, 0x14, state->lo4 | state->fcaptrim);
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dib0070_write_reg(state, 0x18, 0x07ff);
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*tune_state = CT_TUNER_STEP_4;
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}
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return ret;
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}
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static int dib0070_set_ctrl_lo5(struct dvb_frontend *fe, u8 vco_bias_trim, u8 hf_div_trim, u8 cp_current, u8 third_order_filt)
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{
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struct dib0070_state *state = fe->tuner_priv;
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u16 lo5 = (third_order_filt << 14) | (0 << 13) | (1 << 12) | (3 << 9) | (cp_current << 6) | (hf_div_trim << 3) | (vco_bias_trim << 0);
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dprintk("CTRL_LO5: 0x%x\n", lo5);
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return dib0070_write_reg(state, 0x15, lo5);
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}
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void dib0070_ctrl_agc_filter(struct dvb_frontend *fe, u8 open)
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{
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struct dib0070_state *state = fe->tuner_priv;
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if (open) {
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dib0070_write_reg(state, 0x1b, 0xff00);
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dib0070_write_reg(state, 0x1a, 0x0000);
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} else {
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dib0070_write_reg(state, 0x1b, 0x4112);
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if (state->cfg->vga_filter != 0) {
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dib0070_write_reg(state, 0x1a, state->cfg->vga_filter);
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dprintk("vga filter register is set to %x\n", state->cfg->vga_filter);
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} else
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dib0070_write_reg(state, 0x1a, 0x0009);
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}
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}
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EXPORT_SYMBOL(dib0070_ctrl_agc_filter);
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struct dib0070_tuning {
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u32 max_freq; /* for every frequency less than or equal to that field: this information is correct */
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u8 switch_trim;
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u8 vco_band;
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u8 hfdiv;
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u8 vco_multi;
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u8 presc;
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u8 wbdmux;
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u16 tuner_enable;
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};
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struct dib0070_lna_match {
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u32 max_freq; /* for every frequency less than or equal to that field: this information is correct */
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u8 lna_band;
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};
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static const struct dib0070_tuning dib0070s_tuning_table[] = {
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{ 570000, 2, 1, 3, 6, 6, 2, 0x4000 | 0x0800 }, /* UHF */
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{ 700000, 2, 0, 2, 4, 2, 2, 0x4000 | 0x0800 },
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{ 863999, 2, 1, 2, 4, 2, 2, 0x4000 | 0x0800 },
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{ 1500000, 0, 1, 1, 2, 2, 4, 0x2000 | 0x0400 }, /* LBAND */
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{ 1600000, 0, 1, 1, 2, 2, 4, 0x2000 | 0x0400 },
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{ 2000000, 0, 1, 1, 2, 2, 4, 0x2000 | 0x0400 },
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{ 0xffffffff, 0, 0, 8, 1, 2, 1, 0x8000 | 0x1000 }, /* SBAND */
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};
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static const struct dib0070_tuning dib0070_tuning_table[] = {
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{ 115000, 1, 0, 7, 24, 2, 1, 0x8000 | 0x1000 }, /* FM below 92MHz cannot be tuned */
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{ 179500, 1, 0, 3, 16, 2, 1, 0x8000 | 0x1000 }, /* VHF */
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{ 189999, 1, 1, 3, 16, 2, 1, 0x8000 | 0x1000 },
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{ 250000, 1, 0, 6, 12, 2, 1, 0x8000 | 0x1000 },
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{ 569999, 2, 1, 5, 6, 2, 2, 0x4000 | 0x0800 }, /* UHF */
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{ 699999, 2, 0, 1, 4, 2, 2, 0x4000 | 0x0800 },
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{ 863999, 2, 1, 1, 4, 2, 2, 0x4000 | 0x0800 },
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{ 0xffffffff, 0, 1, 0, 2, 2, 4, 0x2000 | 0x0400 }, /* LBAND or everything higher than UHF */
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};
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static const struct dib0070_lna_match dib0070_lna_flip_chip[] = {
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{ 180000, 0 }, /* VHF */
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{ 188000, 1 },
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{ 196400, 2 },
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{ 250000, 3 },
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{ 550000, 0 }, /* UHF */
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{ 590000, 1 },
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{ 666000, 3 },
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{ 864000, 5 },
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{ 1500000, 0 }, /* LBAND or everything higher than UHF */
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{ 1600000, 1 },
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{ 2000000, 3 },
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{ 0xffffffff, 7 },
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};
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static const struct dib0070_lna_match dib0070_lna[] = {
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{ 180000, 0 }, /* VHF */
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{ 188000, 1 },
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{ 196400, 2 },
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{ 250000, 3 },
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{ 550000, 2 }, /* UHF */
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{ 650000, 3 },
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{ 750000, 5 },
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{ 850000, 6 },
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{ 864000, 7 },
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{ 1500000, 0 }, /* LBAND or everything higher than UHF */
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{ 1600000, 1 },
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{ 2000000, 3 },
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{ 0xffffffff, 7 },
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};
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#define LPF 100
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static int dib0070_tune_digital(struct dvb_frontend *fe)
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{
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struct dib0070_state *state = fe->tuner_priv;
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const struct dib0070_tuning *tune;
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const struct dib0070_lna_match *lna_match;
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enum frontend_tune_state *tune_state = &state->tune_state;
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int ret = 10; /* 1ms is the default delay most of the time */
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u8 band = (u8)BAND_OF_FREQUENCY(fe->dtv_property_cache.frequency/1000);
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u32 freq = fe->dtv_property_cache.frequency/1000 + (band == BAND_VHF ? state->cfg->freq_offset_khz_vhf : state->cfg->freq_offset_khz_uhf);
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#ifdef CONFIG_SYS_ISDBT
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if (state->fe->dtv_property_cache.delivery_system == SYS_ISDBT && state->fe->dtv_property_cache.isdbt_sb_mode == 1)
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if (((state->fe->dtv_property_cache.isdbt_sb_segment_count % 2)
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&& (state->fe->dtv_property_cache.isdbt_sb_segment_idx == ((state->fe->dtv_property_cache.isdbt_sb_segment_count / 2) + 1)))
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|| (((state->fe->dtv_property_cache.isdbt_sb_segment_count % 2) == 0)
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&& (state->fe->dtv_property_cache.isdbt_sb_segment_idx == (state->fe->dtv_property_cache.isdbt_sb_segment_count / 2)))
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|| (((state->fe->dtv_property_cache.isdbt_sb_segment_count % 2) == 0)
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&& (state->fe->dtv_property_cache.isdbt_sb_segment_idx == ((state->fe->dtv_property_cache.isdbt_sb_segment_count / 2) + 1))))
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freq += 850;
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#endif
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if (state->current_rf != freq) {
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switch (state->revision) {
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case DIB0070S_P1A:
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tune = dib0070s_tuning_table;
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lna_match = dib0070_lna;
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break;
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default:
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tune = dib0070_tuning_table;
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if (state->cfg->flip_chip)
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lna_match = dib0070_lna_flip_chip;
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else
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lna_match = dib0070_lna;
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break;
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}
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while (freq > tune->max_freq) /* find the right one */
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tune++;
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while (freq > lna_match->max_freq) /* find the right one */
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lna_match++;
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state->current_tune_table_index = tune;
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state->lna_match = lna_match;
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}
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if (*tune_state == CT_TUNER_START) {
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dprintk("Tuning for Band: %hd (%d kHz)\n", band, freq);
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if (state->current_rf != freq) {
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u8 REFDIV;
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u32 FBDiv, Rest, FREF, VCOF_kHz;
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u8 Den;
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state->current_rf = freq;
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state->lo4 = (state->current_tune_table_index->vco_band << 11) | (state->current_tune_table_index->hfdiv << 7);
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dib0070_write_reg(state, 0x17, 0x30);
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VCOF_kHz = state->current_tune_table_index->vco_multi * freq * 2;
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switch (band) {
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case BAND_VHF:
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REFDIV = (u8) ((state->cfg->clock_khz + 9999) / 10000);
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break;
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case BAND_FM:
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REFDIV = (u8) ((state->cfg->clock_khz) / 1000);
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break;
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default:
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REFDIV = (u8) (state->cfg->clock_khz / 10000);
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break;
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}
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FREF = state->cfg->clock_khz / REFDIV;
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switch (state->revision) {
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case DIB0070S_P1A:
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FBDiv = (VCOF_kHz / state->current_tune_table_index->presc / FREF);
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Rest = (VCOF_kHz / state->current_tune_table_index->presc) - FBDiv * FREF;
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break;
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case DIB0070_P1G:
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case DIB0070_P1F:
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default:
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FBDiv = (freq / (FREF / 2));
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Rest = 2 * freq - FBDiv * FREF;
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break;
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}
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if (Rest < LPF)
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Rest = 0;
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else if (Rest < 2 * LPF)
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Rest = 2 * LPF;
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else if (Rest > (FREF - LPF)) {
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Rest = 0;
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FBDiv += 1;
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} else if (Rest > (FREF - 2 * LPF))
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Rest = FREF - 2 * LPF;
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Rest = (Rest * 6528) / (FREF / 10);
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Den = 1;
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if (Rest > 0) {
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state->lo4 |= (1 << 14) | (1 << 12);
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Den = 255;
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}
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dib0070_write_reg(state, 0x11, (u16)FBDiv);
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dib0070_write_reg(state, 0x12, (Den << 8) | REFDIV);
|
|
dib0070_write_reg(state, 0x13, (u16) Rest);
|
|
|
|
if (state->revision == DIB0070S_P1A) {
|
|
|
|
if (band == BAND_SBAND) {
|
|
dib0070_set_ctrl_lo5(fe, 2, 4, 3, 0);
|
|
dib0070_write_reg(state, 0x1d, 0xFFFF);
|
|
} else
|
|
dib0070_set_ctrl_lo5(fe, 5, 4, 3, 1);
|
|
}
|
|
|
|
dib0070_write_reg(state, 0x20,
|
|
0x0040 | 0x0020 | 0x0010 | 0x0008 | 0x0002 | 0x0001 | state->current_tune_table_index->tuner_enable);
|
|
|
|
dprintk("REFDIV: %hd, FREF: %d\n", REFDIV, FREF);
|
|
dprintk("FBDIV: %d, Rest: %d\n", FBDiv, Rest);
|
|
dprintk("Num: %hd, Den: %hd, SD: %hd\n", (u16) Rest, Den, (state->lo4 >> 12) & 0x1);
|
|
dprintk("HFDIV code: %hd\n", state->current_tune_table_index->hfdiv);
|
|
dprintk("VCO = %hd\n", state->current_tune_table_index->vco_band);
|
|
dprintk("VCOF: ((%hd*%d) << 1))\n", state->current_tune_table_index->vco_multi, freq);
|
|
|
|
*tune_state = CT_TUNER_STEP_0;
|
|
} else { /* we are already tuned to this frequency - the configuration is correct */
|
|
ret = 50; /* wakeup time */
|
|
*tune_state = CT_TUNER_STEP_5;
|
|
}
|
|
} else if ((*tune_state > CT_TUNER_START) && (*tune_state < CT_TUNER_STEP_4)) {
|
|
|
|
ret = dib0070_captrim(state, tune_state);
|
|
|
|
} else if (*tune_state == CT_TUNER_STEP_4) {
|
|
const struct dib0070_wbd_gain_cfg *tmp = state->cfg->wbd_gain;
|
|
if (tmp != NULL) {
|
|
while (freq/1000 > tmp->freq) /* find the right one */
|
|
tmp++;
|
|
dib0070_write_reg(state, 0x0f,
|
|
(0 << 15) | (1 << 14) | (3 << 12)
|
|
| (tmp->wbd_gain_val << 9) | (0 << 8) | (1 << 7)
|
|
| (state->current_tune_table_index->wbdmux << 0));
|
|
state->wbd_gain_current = tmp->wbd_gain_val;
|
|
} else {
|
|
dib0070_write_reg(state, 0x0f,
|
|
(0 << 15) | (1 << 14) | (3 << 12)
|
|
| (6 << 9) | (0 << 8) | (1 << 7)
|
|
| (state->current_tune_table_index->wbdmux << 0));
|
|
state->wbd_gain_current = 6;
|
|
}
|
|
|
|
dib0070_write_reg(state, 0x06, 0x3fff);
|
|
dib0070_write_reg(state, 0x07,
|
|
(state->current_tune_table_index->switch_trim << 11) | (7 << 8) | (state->lna_match->lna_band << 3) | (3 << 0));
|
|
dib0070_write_reg(state, 0x08, (state->lna_match->lna_band << 10) | (3 << 7) | (127));
|
|
dib0070_write_reg(state, 0x0d, 0x0d80);
|
|
|
|
|
|
dib0070_write_reg(state, 0x18, 0x07ff);
|
|
dib0070_write_reg(state, 0x17, 0x0033);
|
|
|
|
|
|
*tune_state = CT_TUNER_STEP_5;
|
|
} else if (*tune_state == CT_TUNER_STEP_5) {
|
|
dib0070_set_bandwidth(fe);
|
|
*tune_state = CT_TUNER_STOP;
|
|
} else {
|
|
ret = FE_CALLBACK_TIME_NEVER; /* tuner finished, time to call again infinite */
|
|
}
|
|
return ret;
|
|
}
|
|
|
|
|
|
static int dib0070_tune(struct dvb_frontend *fe)
|
|
{
|
|
struct dib0070_state *state = fe->tuner_priv;
|
|
uint32_t ret;
|
|
|
|
state->tune_state = CT_TUNER_START;
|
|
|
|
do {
|
|
ret = dib0070_tune_digital(fe);
|
|
if (ret != FE_CALLBACK_TIME_NEVER)
|
|
msleep(ret/10);
|
|
else
|
|
break;
|
|
} while (state->tune_state != CT_TUNER_STOP);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int dib0070_wakeup(struct dvb_frontend *fe)
|
|
{
|
|
struct dib0070_state *state = fe->tuner_priv;
|
|
if (state->cfg->sleep)
|
|
state->cfg->sleep(fe, 0);
|
|
return 0;
|
|
}
|
|
|
|
static int dib0070_sleep(struct dvb_frontend *fe)
|
|
{
|
|
struct dib0070_state *state = fe->tuner_priv;
|
|
if (state->cfg->sleep)
|
|
state->cfg->sleep(fe, 1);
|
|
return 0;
|
|
}
|
|
|
|
u8 dib0070_get_rf_output(struct dvb_frontend *fe)
|
|
{
|
|
struct dib0070_state *state = fe->tuner_priv;
|
|
return (dib0070_read_reg(state, 0x07) >> 11) & 0x3;
|
|
}
|
|
EXPORT_SYMBOL(dib0070_get_rf_output);
|
|
|
|
int dib0070_set_rf_output(struct dvb_frontend *fe, u8 no)
|
|
{
|
|
struct dib0070_state *state = fe->tuner_priv;
|
|
u16 rxrf2 = dib0070_read_reg(state, 0x07) & 0xfe7ff;
|
|
if (no > 3)
|
|
no = 3;
|
|
if (no < 1)
|
|
no = 1;
|
|
return dib0070_write_reg(state, 0x07, rxrf2 | (no << 11));
|
|
}
|
|
EXPORT_SYMBOL(dib0070_set_rf_output);
|
|
|
|
static const u16 dib0070_p1f_defaults[] =
|
|
|
|
{
|
|
7, 0x02,
|
|
0x0008,
|
|
0x0000,
|
|
0x0000,
|
|
0x0000,
|
|
0x0000,
|
|
0x0002,
|
|
0x0100,
|
|
|
|
3, 0x0d,
|
|
0x0d80,
|
|
0x0001,
|
|
0x0000,
|
|
|
|
4, 0x11,
|
|
0x0000,
|
|
0x0103,
|
|
0x0000,
|
|
0x0000,
|
|
|
|
3, 0x16,
|
|
0x0004 | 0x0040,
|
|
0x0030,
|
|
0x07ff,
|
|
|
|
6, 0x1b,
|
|
0x4112,
|
|
0xff00,
|
|
0xc07f,
|
|
0x0000,
|
|
0x0180,
|
|
0x4000 | 0x0800 | 0x0040 | 0x0020 | 0x0010 | 0x0008 | 0x0002 | 0x0001,
|
|
|
|
0,
|
|
};
|
|
|
|
static u16 dib0070_read_wbd_offset(struct dib0070_state *state, u8 gain)
|
|
{
|
|
u16 tuner_en = dib0070_read_reg(state, 0x20);
|
|
u16 offset;
|
|
|
|
dib0070_write_reg(state, 0x18, 0x07ff);
|
|
dib0070_write_reg(state, 0x20, 0x0800 | 0x4000 | 0x0040 | 0x0020 | 0x0010 | 0x0008 | 0x0002 | 0x0001);
|
|
dib0070_write_reg(state, 0x0f, (1 << 14) | (2 << 12) | (gain << 9) | (1 << 8) | (1 << 7) | (0 << 0));
|
|
msleep(9);
|
|
offset = dib0070_read_reg(state, 0x19);
|
|
dib0070_write_reg(state, 0x20, tuner_en);
|
|
return offset;
|
|
}
|
|
|
|
static void dib0070_wbd_offset_calibration(struct dib0070_state *state)
|
|
{
|
|
u8 gain;
|
|
for (gain = 6; gain < 8; gain++) {
|
|
state->wbd_offset_3_3[gain - 6] = ((dib0070_read_wbd_offset(state, gain) * 8 * 18 / 33 + 1) / 2);
|
|
dprintk("Gain: %d, WBDOffset (3.3V) = %hd\n", gain, state->wbd_offset_3_3[gain-6]);
|
|
}
|
|
}
|
|
|
|
u16 dib0070_wbd_offset(struct dvb_frontend *fe)
|
|
{
|
|
struct dib0070_state *state = fe->tuner_priv;
|
|
const struct dib0070_wbd_gain_cfg *tmp = state->cfg->wbd_gain;
|
|
u32 freq = fe->dtv_property_cache.frequency/1000;
|
|
|
|
if (tmp != NULL) {
|
|
while (freq/1000 > tmp->freq) /* find the right one */
|
|
tmp++;
|
|
state->wbd_gain_current = tmp->wbd_gain_val;
|
|
} else
|
|
state->wbd_gain_current = 6;
|
|
|
|
return state->wbd_offset_3_3[state->wbd_gain_current - 6];
|
|
}
|
|
EXPORT_SYMBOL(dib0070_wbd_offset);
|
|
|
|
#define pgm_read_word(w) (*w)
|
|
static int dib0070_reset(struct dvb_frontend *fe)
|
|
{
|
|
struct dib0070_state *state = fe->tuner_priv;
|
|
u16 l, r, *n;
|
|
|
|
HARD_RESET(state);
|
|
|
|
|
|
#ifndef FORCE_SBAND_TUNER
|
|
if ((dib0070_read_reg(state, 0x22) >> 9) & 0x1)
|
|
state->revision = (dib0070_read_reg(state, 0x1f) >> 8) & 0xff;
|
|
else
|
|
#else
|
|
#warning forcing SBAND
|
|
#endif
|
|
state->revision = DIB0070S_P1A;
|
|
|
|
/* P1F or not */
|
|
dprintk("Revision: %x\n", state->revision);
|
|
|
|
if (state->revision == DIB0070_P1D) {
|
|
dprintk("Error: this driver is not to be used meant for P1D or earlier\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
n = (u16 *) dib0070_p1f_defaults;
|
|
l = pgm_read_word(n++);
|
|
while (l) {
|
|
r = pgm_read_word(n++);
|
|
do {
|
|
dib0070_write_reg(state, (u8)r, pgm_read_word(n++));
|
|
r++;
|
|
} while (--l);
|
|
l = pgm_read_word(n++);
|
|
}
|
|
|
|
if (state->cfg->force_crystal_mode != 0)
|
|
r = state->cfg->force_crystal_mode;
|
|
else if (state->cfg->clock_khz >= 24000)
|
|
r = 1;
|
|
else
|
|
r = 2;
|
|
|
|
|
|
r |= state->cfg->osc_buffer_state << 3;
|
|
|
|
dib0070_write_reg(state, 0x10, r);
|
|
dib0070_write_reg(state, 0x1f, (1 << 8) | ((state->cfg->clock_pad_drive & 0xf) << 5));
|
|
|
|
if (state->cfg->invert_iq) {
|
|
r = dib0070_read_reg(state, 0x02) & 0xffdf;
|
|
dib0070_write_reg(state, 0x02, r | (1 << 5));
|
|
}
|
|
|
|
if (state->revision == DIB0070S_P1A)
|
|
dib0070_set_ctrl_lo5(fe, 2, 4, 3, 0);
|
|
else
|
|
dib0070_set_ctrl_lo5(fe, 5, 4, state->cfg->charge_pump,
|
|
state->cfg->enable_third_order_filter);
|
|
|
|
dib0070_write_reg(state, 0x01, (54 << 9) | 0xc8);
|
|
|
|
dib0070_wbd_offset_calibration(state);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int dib0070_get_frequency(struct dvb_frontend *fe, u32 *frequency)
|
|
{
|
|
struct dib0070_state *state = fe->tuner_priv;
|
|
|
|
*frequency = 1000 * state->current_rf;
|
|
return 0;
|
|
}
|
|
|
|
static void dib0070_release(struct dvb_frontend *fe)
|
|
{
|
|
kfree(fe->tuner_priv);
|
|
fe->tuner_priv = NULL;
|
|
}
|
|
|
|
static const struct dvb_tuner_ops dib0070_ops = {
|
|
.info = {
|
|
.name = "DiBcom DiB0070",
|
|
.frequency_min = 45000000,
|
|
.frequency_max = 860000000,
|
|
.frequency_step = 1000,
|
|
},
|
|
.release = dib0070_release,
|
|
|
|
.init = dib0070_wakeup,
|
|
.sleep = dib0070_sleep,
|
|
.set_params = dib0070_tune,
|
|
|
|
.get_frequency = dib0070_get_frequency,
|
|
// .get_bandwidth = dib0070_get_bandwidth
|
|
};
|
|
|
|
struct dvb_frontend *dib0070_attach(struct dvb_frontend *fe, struct i2c_adapter *i2c, struct dib0070_config *cfg)
|
|
{
|
|
struct dib0070_state *state = kzalloc(sizeof(struct dib0070_state), GFP_KERNEL);
|
|
if (state == NULL)
|
|
return NULL;
|
|
|
|
state->cfg = cfg;
|
|
state->i2c = i2c;
|
|
state->fe = fe;
|
|
mutex_init(&state->i2c_buffer_lock);
|
|
fe->tuner_priv = state;
|
|
|
|
if (dib0070_reset(fe) != 0)
|
|
goto free_mem;
|
|
|
|
pr_info("DiB0070: successfully identified\n");
|
|
memcpy(&fe->ops.tuner_ops, &dib0070_ops, sizeof(struct dvb_tuner_ops));
|
|
|
|
fe->tuner_priv = state;
|
|
return fe;
|
|
|
|
free_mem:
|
|
kfree(state);
|
|
fe->tuner_priv = NULL;
|
|
return NULL;
|
|
}
|
|
EXPORT_SYMBOL(dib0070_attach);
|
|
|
|
MODULE_AUTHOR("Patrick Boettcher <patrick.boettcher@posteo.de>");
|
|
MODULE_DESCRIPTION("Driver for the DiBcom 0070 base-band RF Tuner");
|
|
MODULE_LICENSE("GPL");
|