forked from Minki/linux
e18287d301
Patch b6d1c33a31 "ARM: Orion: Consolidate the address map setup" tried
to merge the address map for the four orion platforms, but apparently
got it wrong for mv78xx0. Admittedly I don't understand what this
code actually does, but it's clear that the current version is
wrong.
Without this patch, building mv78xx0_defconfig results in:
arch/arm/mach-mv78xx0/addr-map.c:59:2: warning: initialization from incompatible pointer type [enabled by default]
arch/arm/mach-mv78xx0/addr-map.c:59:2: warning: (near initialization for 'addr_map_cfg.win_cfg_base') [enabled by default]
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Andrew Lunn <andrew@lunn.ch>
Cc: Michael Walle <michael@walle.cc>
Cc: Nicolas Pitre <nico@linaro.org>
93 lines
2.4 KiB
C
93 lines
2.4 KiB
C
/*
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* arch/arm/mach-mv78xx0/addr-map.c
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*
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* Address map functions for Marvell MV78xx0 SoCs
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/mbus.h>
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#include <linux/io.h>
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#include <plat/addr-map.h>
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#include "common.h"
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/*
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* Generic Address Decode Windows bit settings
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*/
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#define TARGET_DEV_BUS 1
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#define TARGET_PCIE0 4
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#define TARGET_PCIE1 8
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#define TARGET_PCIE(i) ((i) ? TARGET_PCIE1 : TARGET_PCIE0)
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#define ATTR_DEV_SPI_ROM 0x1f
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#define ATTR_DEV_BOOT 0x2f
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#define ATTR_DEV_CS3 0x37
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#define ATTR_DEV_CS2 0x3b
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#define ATTR_DEV_CS1 0x3d
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#define ATTR_DEV_CS0 0x3e
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#define ATTR_PCIE_IO(l) (0xf0 & ~(0x10 << (l)))
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#define ATTR_PCIE_MEM(l) (0xf8 & ~(0x10 << (l)))
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/*
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* CPU Address Decode Windows registers
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*/
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#define WIN0_OFF(n) (BRIDGE_VIRT_BASE + 0x0000 + ((n) << 4))
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#define WIN8_OFF(n) (BRIDGE_VIRT_BASE + 0x0900 + (((n) - 8) << 4))
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static void __init __iomem *win_cfg_base(const struct orion_addr_map_cfg *cfg, int win)
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{
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/*
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* Find the control register base address for this window.
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*
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* BRIDGE_VIRT_BASE points to the right (CPU0's or CPU1's)
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* MBUS bridge depending on which CPU core we're running on,
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* so we don't need to take that into account here.
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*/
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return (void __iomem *)((win < 8) ? WIN0_OFF(win) : WIN8_OFF(win));
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}
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/*
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* Description of the windows needed by the platform code
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*/
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static struct __initdata orion_addr_map_cfg addr_map_cfg = {
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.num_wins = 14,
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.remappable_wins = 8,
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.win_cfg_base = win_cfg_base,
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};
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void __init mv78xx0_setup_cpu_mbus(void)
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{
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/*
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* Disable, clear and configure windows.
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*/
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orion_config_wins(&addr_map_cfg, NULL);
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/*
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* Setup MBUS dram target info.
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*/
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if (mv78xx0_core_index() == 0)
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orion_setup_cpu_mbus_target(&addr_map_cfg,
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DDR_WINDOW_CPU0_BASE);
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else
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orion_setup_cpu_mbus_target(&addr_map_cfg,
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DDR_WINDOW_CPU1_BASE);
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}
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void __init mv78xx0_setup_pcie_io_win(int window, u32 base, u32 size,
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int maj, int min)
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{
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orion_setup_cpu_win(&addr_map_cfg, window, base, size,
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TARGET_PCIE(maj), ATTR_PCIE_IO(min), -1);
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}
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void __init mv78xx0_setup_pcie_mem_win(int window, u32 base, u32 size,
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int maj, int min)
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{
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orion_setup_cpu_win(&addr_map_cfg, window, base, size,
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TARGET_PCIE(maj), ATTR_PCIE_MEM(min), -1);
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}
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