Abhinav Kumar 2d0b10fc51 drm/msm: higher values of pclk can exceed 32 bits when multiplied by a factor ... Make the pclk_rate u64 to accommodate higher pixel clock rates. Changes in v3: - Converted pclk_rate to u32 (Archit) - Rebase on dsi cleanup set in msm-next Cc: Sibi Sankar <sibis@codeaurora.org> Cc: Archit Taneja <architt@codeaurora.org> Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org> Signed-off-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Rob Clark <robdclark@gmail.com>		2018-07-26 10:40:15 -04:00
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phy	drm/msm/dsi: implement auto PHY timing calculator for 10nm PHY	2018-06-03 16:48:59 -04:00
pll	drm/msm/dsi: initialize postdiv_lock before use for 10nm pll	2018-07-26 10:40:14 -04:00
dsi_cfg.c	drm/msm/dsi: add implementation for helper functions	2018-07-25 07:51:04 -04:00
dsi_cfg.h	drm/msm/dsi: adjust dsi timing for dual dsi mode	2018-07-26 10:40:14 -04:00
dsi_host.c	drm/msm: higher values of pclk can exceed 32 bits when multiplied by a factor	2018-07-26 10:40:15 -04:00
dsi_manager.c	drm/msm/dsi: set encoder mode for DRM bridge explicitly	2018-07-26 10:40:14 -04:00
dsi.c	drm/msm/dsi: Use one connector for dual DSI mode	2018-07-26 10:40:14 -04:00
dsi.h	drm/msm/dsi: Use one connector for dual DSI mode	2018-07-26 10:40:14 -04:00
dsi.xml.h	drm/msm/dsi: Update generated headers for 10nm PLL/PHY	2018-02-20 10:41:20 -05:00
mmss_cc.xml.h	drm/msm: update generated headers	2017-06-16 11:16:07 -04:00
sfpb.xml.h	drm/msm: update generated headers	2017-06-16 11:16:07 -04:00