Sergio Paracuellos 5ca61dffc7 staging: mt7621-pci: enable clock bit for each port ... The clock related code concerns me from the very beginning because there are some set ups got from legacy driver that are not documented anywhere. According to the programming guide 0x7c is 'CPE_ROSC_SEL1' register and 0x80 is 'CPU_CPE_CN'. I do think this set up is not needed at all and the proper thing to do is just enable the clock bit for each pcie port. Hence remove useless code and do the right thing which is setting up the clock bit for each port enabled. Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20200310113459.30539-1-sergio.paracuellos@gmail.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>		2020-03-11 08:08:48 +01:00
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Kconfig	MIPS: ralink: enable PCI support only if driver for mt7621 SoC is selected	2019-11-14 13:09:37 +08:00
Makefile	staging: add missing SPDX lines to Makefile files	2019-04-03 11:10:15 +02:00
mediatek,mt7621-pci.txt	staging: mt7621-pci: dt-bindings: add perst-gpio to sample bindings	2019-06-20 14:45:50 +02:00
pci-mt7621.c	staging: mt7621-pci: enable clock bit for each port	2020-03-11 08:08:48 +01:00
TODO	staging: mt7621-pci: update driver's TODO file	2019-02-11 10:02:50 +01:00