forked from Minki/linux
97d4b35fb4
I have a system where UART0 is configured with hardware flow control, but UART1
doesn't have it enabled. Attempting to access UART1 in this configuration
results in the following error in dmesg:
<3>bfin-gpio: GPIO 0 is already reserved as Peripheral by bfin-uart !
<5>Stack from 0082bc7c:
<5> 0082bc88 00404dd6 00000003 00000000 0054051e 004079da 0082bcb4
00000000
<5> 00000003 00000000 0052686c 0113f2a0 005fa3f0 00000032 20515249
00003035
<5> 00427228 00526e50 0113f2e0 005fa3f0 00000032 0113f2e0 0054b748
0000ffff
<5> 22222222 22222222 004e1628 00427304 00000000 00000032 00000023
0054b748
<5> 00487a94 0054b7e8 0054b748 0000000b 00487fb8 0054b748 0054b748
00000001
<5> 0000000a 005fa3f0 009d4fe8 0101e3c0 0054b748 005fa3f0 0050b134
0054b748
<5>
<5>Call Trace:
<4>[<00485c16>] _uart_startup+0x56/0x178
<4>[<004865c8>] _uart_open+0x40/0x3e0
<4>[<0048661c>] _uart_open+0x94/0x3e0
<4>[<0047f1ce>] _init_dev+0x1fa/0x450
<4>[<004e1628>] ___mutex_unlock_slowpath+0x30/0xe8
<4>[<004815da>] _tty_open+0xf6/0x21c
<4>[<0043dab0>] ___path_lookup_intent_open+0x34/0x7c
<4>[<004375e4>] _chrdev_open+0x7c/0x134
<4>[<0043dc2c>] _open_namei+0x60/0x568
<4>[<00433fa2>] ___dentry_open+0x9e/0x188
<4>[<00437568>] _chrdev_open+0x0/0x134
<4>[<0043410c>] _nameidata_to_filp+0x30/0x3c
<4>[<00434152>] _do_filp_open+0x3a/0x44
<4>[<00408826>] _task_running_tick+0x102/0x278
<4>[<0043418e>] _do_sys_open+0x32/0xac
<4>[<0043ede4>] _sys_ioctl+0x28/0x50
<4>[<0043edbc>] _sys_ioctl+0x0/0x50
<4>[<00434224>] _sys_open+0x18/0x20
<4>[<0043420c>] _sys_open+0x0/0x20
<4>[<00418174>] _sys_setuid+0x0/0xc8
This is because the #ifdef's in bfin_serial_5xx.h are messed up. More
specifically, they add/remove the uart_{rts,cts}_pin fields in
bfin_serial_resources based on whether the particular port has rts/cts enabled,
as opposed to when either port has it enabled.
This patch fixed this.
Signed-off-by: Tom Parker <blackfin@tevp.net>
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
196 lines
5.5 KiB
C
196 lines
5.5 KiB
C
/*
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* file: include/asm-blackfin/mach-bf527/bfin_serial_5xx.h
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* based on:
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* author:
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*
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* created:
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* description:
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* blackfin serial driver head file
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* rev:
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*
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* modified:
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*
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*
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* bugs: enter bugs at http://blackfin.uclinux.org/
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*
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* this program is free software; you can redistribute it and/or modify
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* it under the terms of the gnu general public license as published by
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* the free software foundation; either version 2, or (at your option)
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* any later version.
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*
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* this program is distributed in the hope that it will be useful,
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* but without any warranty; without even the implied warranty of
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* merchantability or fitness for a particular purpose. see the
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* gnu general public license for more details.
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*
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* you should have received a copy of the gnu general public license
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* along with this program; see the file copying.
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* if not, write to the free software foundation,
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* 59 temple place - suite 330, boston, ma 02111-1307, usa.
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*/
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#include <linux/serial.h>
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#include <asm/dma.h>
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#include <asm/portmux.h>
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#define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR))
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#define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL))
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#define UART_GET_IER(uart) bfin_read16(((uart)->port.membase + OFFSET_IER))
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#define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH))
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#define UART_GET_IIR(uart) bfin_read16(((uart)->port.membase + OFFSET_IIR))
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#define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR))
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#define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL))
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#define UART_PUT_CHAR(uart, v) bfin_write16(((uart)->port.membase + OFFSET_THR), v)
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#define UART_PUT_DLL(uart, v) bfin_write16(((uart)->port.membase + OFFSET_DLL), v)
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#define UART_PUT_IER(uart, v) bfin_write16(((uart)->port.membase + OFFSET_IER), v)
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#define UART_SET_IER(uart, v) UART_PUT_IER(uart, UART_GET_IER(uart) | (v))
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#define UART_CLEAR_IER(uart, v) UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v))
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#define UART_PUT_DLH(uart, v) bfin_write16(((uart)->port.membase + OFFSET_DLH), v)
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#define UART_PUT_LCR(uart, v) bfin_write16(((uart)->port.membase + OFFSET_LCR), v)
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#define UART_PUT_GCTL(uart, v) bfin_write16(((uart)->port.membase + OFFSET_GCTL), v)
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#define UART_SET_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0)
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#define UART_CLEAR_DLAB(uart) do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0)
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#define UART_GET_CTS(x) gpio_get_value(x->cts_pin)
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#define UART_SET_RTS(x) gpio_set_value(x->rts_pin, 1)
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#define UART_CLEAR_RTS(x) gpio_set_value(x->rts_pin, 0)
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#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
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#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0)
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#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS)
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# define CONFIG_SERIAL_BFIN_CTSRTS
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# ifndef CONFIG_UART0_CTS_PIN
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# define CONFIG_UART0_CTS_PIN -1
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# endif
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# ifndef CONFIG_UART0_RTS_PIN
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# define CONFIG_UART0_RTS_PIN -1
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# endif
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# ifndef CONFIG_UART1_CTS_PIN
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# define CONFIG_UART1_CTS_PIN -1
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# endif
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# ifndef CONFIG_UART1_RTS_PIN
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# define CONFIG_UART1_RTS_PIN -1
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# endif
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#endif
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#define BFIN_UART_TX_FIFO_SIZE 2
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/*
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* The pin configuration is different from schematic
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*/
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struct bfin_serial_port {
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struct uart_port port;
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unsigned int old_status;
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unsigned int lsr;
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#ifdef CONFIG_SERIAL_BFIN_DMA
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int tx_done;
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int tx_count;
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struct circ_buf rx_dma_buf;
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struct timer_list rx_dma_timer;
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int rx_dma_nrows;
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unsigned int tx_dma_channel;
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unsigned int rx_dma_channel;
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struct work_struct tx_dma_workqueue;
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#endif
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#ifdef CONFIG_SERIAL_BFIN_CTSRTS
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struct timer_list cts_timer;
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int cts_pin;
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int rts_pin;
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#endif
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};
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/* The hardware clears the LSR bits upon read, so we need to cache
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* some of the more fun bits in software so they don't get lost
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* when checking the LSR in other code paths (TX).
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*/
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static inline unsigned int UART_GET_LSR(struct bfin_serial_port *uart)
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{
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unsigned int lsr = bfin_read16(uart->port.membase + OFFSET_LSR);
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uart->lsr |= (lsr & (BI|FE|PE|OE));
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return lsr | uart->lsr;
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}
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static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart)
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{
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uart->lsr = 0;
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bfin_write16(uart->port.membase + OFFSET_LSR, -1);
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}
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struct bfin_serial_res {
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unsigned long uart_base_addr;
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int uart_irq;
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#ifdef CONFIG_SERIAL_BFIN_DMA
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unsigned int uart_tx_dma_channel;
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unsigned int uart_rx_dma_channel;
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#endif
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#ifdef CONFIG_SERIAL_BFIN_CTSRTS
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int uart_cts_pin;
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int uart_rts_pin;
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#endif
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};
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struct bfin_serial_res bfin_serial_resource[] = {
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#ifdef CONFIG_SERIAL_BFIN_UART0
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{
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0xFFC00400,
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IRQ_UART0_RX,
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#ifdef CONFIG_SERIAL_BFIN_DMA
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CH_UART0_TX,
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CH_UART0_RX,
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#endif
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#ifdef CONFIG_SERIAL_BFIN_CTSRTS
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CONFIG_UART0_CTS_PIN,
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CONFIG_UART0_RTS_PIN,
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#endif
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},
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#endif
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#ifdef CONFIG_SERIAL_BFIN_UART1
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{
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0xFFC02000,
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IRQ_UART1_RX,
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#ifdef CONFIG_SERIAL_BFIN_DMA
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CH_UART1_TX,
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CH_UART1_RX,
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#endif
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#ifdef CONFIG_SERIAL_BFIN_CTSRTS
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CONFIG_UART1_CTS_PIN,
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CONFIG_UART1_RTS_PIN,
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#endif
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},
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#endif
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};
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#define DRIVER_NAME "bfin-uart"
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static void bfin_serial_hw_init(struct bfin_serial_port *uart)
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{
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#ifdef CONFIG_SERIAL_BFIN_UART0
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peripheral_request(P_UART0_TX, DRIVER_NAME);
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peripheral_request(P_UART0_RX, DRIVER_NAME);
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#endif
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#ifdef CONFIG_SERIAL_BFIN_UART1
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peripheral_request(P_UART1_TX, DRIVER_NAME);
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peripheral_request(P_UART1_RX, DRIVER_NAME);
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#endif
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#ifdef CONFIG_SERIAL_BFIN_CTSRTS
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if (uart->cts_pin >= 0) {
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gpio_request(uart->cts_pin, DRIVER_NAME);
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gpio_direction_input(uart->cts_pin);
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}
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if (uart->rts_pin >= 0) {
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gpio_request(uart->rts_pin, DRIVER_NAME);
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gpio_direction_output(uart->rts_pin, 0);
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}
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#endif
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}
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