forked from Minki/linux
3e5907a17f
The LVDCR1 register for the R-Car gen3 SoCs was documented as having the
layout different from the gen2 SoCs in the early R-Car gen3 manuals but
since v0.52 the LVDCR1 layout is described as being the same as on the gen2
SoCs; the old CHn control values are said to be prohibited now (and there
seems to be no valid output signal when they are used).
Fixes: 6bc2e15cf2 ("drm: rcar-du: lvds: Add R-Car Gen3 support")
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Tested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
78 lines
2.6 KiB
C
78 lines
2.6 KiB
C
/*
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* rcar_lvds_regs.h -- R-Car LVDS Interface Registers Definitions
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*
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* Copyright (C) 2013-2015 Renesas Electronics Corporation
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*
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* Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2
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* as published by the Free Software Foundation.
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*/
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#ifndef __RCAR_LVDS_REGS_H__
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#define __RCAR_LVDS_REGS_H__
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#define LVDCR0 0x0000
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#define LVDCR0_DUSEL (1 << 15)
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#define LVDCR0_DMD (1 << 12) /* Gen2 only */
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#define LVDCR0_LVMD_MASK (0xf << 8)
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#define LVDCR0_LVMD_SHIFT 8
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#define LVDCR0_PLLON (1 << 4)
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#define LVDCR0_PWD (1 << 2) /* Gen3 only */
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#define LVDCR0_BEN (1 << 2) /* Gen2 only */
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#define LVDCR0_LVEN (1 << 1) /* Gen2 only */
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#define LVDCR0_LVRES (1 << 0)
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#define LVDCR1 0x0004
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#define LVDCR1_CKSEL (1 << 15) /* Gen2 only */
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#define LVDCR1_CHSTBY(n) (3 << (2 + (n) * 2))
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#define LVDCR1_CLKSTBY (3 << 0)
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#define LVDPLLCR 0x0008
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#define LVDPLLCR_CEEN (1 << 14)
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#define LVDPLLCR_FBEN (1 << 13)
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#define LVDPLLCR_COSEL (1 << 12)
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/* Gen2 */
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#define LVDPLLCR_PLLDLYCNT_150M (0x1bf << 0)
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#define LVDPLLCR_PLLDLYCNT_121M (0x22c << 0)
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#define LVDPLLCR_PLLDLYCNT_60M (0x77b << 0)
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#define LVDPLLCR_PLLDLYCNT_38M (0x69a << 0)
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#define LVDPLLCR_PLLDLYCNT_MASK (0x7ff << 0)
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/* Gen3 */
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#define LVDPLLCR_PLLDIVCNT_42M (0x014cb << 0)
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#define LVDPLLCR_PLLDIVCNT_85M (0x00a45 << 0)
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#define LVDPLLCR_PLLDIVCNT_128M (0x006c3 << 0)
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#define LVDPLLCR_PLLDIVCNT_148M (0x046c1 << 0)
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#define LVDPLLCR_PLLDIVCNT_MASK (0x7ffff << 0)
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#define LVDCTRCR 0x000c
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#define LVDCTRCR_CTR3SEL_ZERO (0 << 12)
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#define LVDCTRCR_CTR3SEL_ODD (1 << 12)
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#define LVDCTRCR_CTR3SEL_CDE (2 << 12)
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#define LVDCTRCR_CTR3SEL_MASK (7 << 12)
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#define LVDCTRCR_CTR2SEL_DISP (0 << 8)
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#define LVDCTRCR_CTR2SEL_ODD (1 << 8)
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#define LVDCTRCR_CTR2SEL_CDE (2 << 8)
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#define LVDCTRCR_CTR2SEL_HSYNC (3 << 8)
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#define LVDCTRCR_CTR2SEL_VSYNC (4 << 8)
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#define LVDCTRCR_CTR2SEL_MASK (7 << 8)
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#define LVDCTRCR_CTR1SEL_VSYNC (0 << 4)
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#define LVDCTRCR_CTR1SEL_DISP (1 << 4)
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#define LVDCTRCR_CTR1SEL_ODD (2 << 4)
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#define LVDCTRCR_CTR1SEL_CDE (3 << 4)
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#define LVDCTRCR_CTR1SEL_HSYNC (4 << 4)
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#define LVDCTRCR_CTR1SEL_MASK (7 << 4)
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#define LVDCTRCR_CTR0SEL_HSYNC (0 << 0)
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#define LVDCTRCR_CTR0SEL_VSYNC (1 << 0)
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#define LVDCTRCR_CTR0SEL_DISP (2 << 0)
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#define LVDCTRCR_CTR0SEL_ODD (3 << 0)
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#define LVDCTRCR_CTR0SEL_CDE (4 << 0)
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#define LVDCTRCR_CTR0SEL_MASK (7 << 0)
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#define LVDCHCR 0x0010
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#define LVDCHCR_CHSEL_CH(n, c) ((((c) - (n)) & 3) << ((n) * 4))
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#define LVDCHCR_CHSEL_MASK(n) (3 << ((n) * 4))
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#endif /* __RCAR_LVDS_REGS_H__ */
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