linux/drivers/clk/socfpga
Colin Ian King 5c58585090 clk: socfpga: remove redundant assignment after a mask operation
The assignment operation after a & mask operation is redundant, the
variables being assigned are not used afterwards. Replace the &=
operator with just & operator.

Cleans up two clang-scan warnings:
drivers/clk/socfpga/clk-gate.c:37:10: warning: Although the value stored
to 'l4_src' is used in the enclosing expression, the value is never
actually read from 'l4_src' [deadcode.DeadStores]
                return l4_src &= 0x1;
                       ^         ~~~
drivers/clk/socfpga/clk-gate.c:46:10: warning: Although the value stored
to 'perpll_src' is used in the enclosing expression, the value is never
actually read from 'perpll_src' [deadcode.DeadStores]
                return perpll_src &= 0x3;

Signed-off-by: Colin Ian King <colin.i.king@gmail.com>
Link: https://lore.kernel.org/r/20211230150321.167576-1-colin.i.king@gmail.com
Acked-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-01-05 16:33:09 -08:00
..
clk-agilex.c clk: socfpga: agilex: fix duplicate s2f_user0_clk 2021-09-24 16:03:08 -07:00
clk-gate-a10.c clk: socfpga: arria10: Fix memory leak of socfpga_clk on error return 2021-04-07 16:29:31 -07:00
clk-gate-s10.c clk: agilex/stratix10: add support for the 2nd bypass 2021-06-27 16:39:59 -07:00
clk-gate.c clk: socfpga: remove redundant assignment after a mask operation 2022-01-05 16:33:09 -08:00
clk-periph-a10.c clk: socfpga: arria10: convert to use clk_hw 2021-03-30 19:26:26 -07:00
clk-periph-s10.c clk: agilex/stratix10/n5x: fix how the bypass_reg is handled 2021-06-27 16:39:59 -07:00
clk-periph.c clk: socfpga: use clk_hw_register for a5/c5 2021-03-30 19:26:26 -07:00
clk-pll-a10.c clk: socfpga: arria10: convert to use clk_hw 2021-03-30 19:26:26 -07:00
clk-pll-s10.c clk: socfpga: remove redundant assignment on division 2022-01-05 16:32:43 -08:00
clk-pll.c clk: socfpga: clk-pll: Remove unused variable 'rc' 2021-06-27 17:33:21 -07:00
clk-s10.c clk: agilex/stratix10: fix bypass representation 2021-06-27 16:39:59 -07:00
clk.c treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 13 2019-05-21 11:28:45 +02:00
clk.h treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 288 2019-06-05 17:36:37 +02:00
Kconfig clk: socfpga: use ARCH_INTEL_SOCFPGA also for 32-bit ARM SoCs (and compile test) 2021-03-23 11:03:36 -05:00
Makefile clk: socfpga: use ARCH_INTEL_SOCFPGA also for 32-bit ARM SoCs (and compile test) 2021-03-23 11:03:36 -05:00
stratix10-clk.h clk: agilex/stratix10: add support for the 2nd bypass 2021-06-27 16:39:59 -07:00