linux/drivers/gpu
Chris Wilson 5bab6f60cb drm/i915: Serialise updates to GGTT with access through GGTT on Braswell
When accessing through the GTT from one CPU whilst concurrently updating
the GGTT PTEs in another thread, the hardware likes to return random
data. As we have strong serialisation prevent us from modifying the PTE
of an active GTT mmapping, we have to conclude that it whilst modifying
other PTE's that error occurs. (I have not looked for any pattern such
as modifying PTE within the same page or cacheline as active PTE -
though checking whether revoking neighbouring objects should be enough
to test that theory.) The corruption also seems restricted to Braswell
and disappears with maxcpus=0. This patch stops all access through the
GTT by other CPUs when we update any PTE by stopping the machine around
the GGTT update.

Note that splitting up the 64 bit write into two 32 bit writes was
tried and found to fail too.

Testcase: igt/gem_concurrent_blit
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89079
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
[danvet: Add note about 2x 32bits failing too.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-11-17 17:36:01 +01:00
..
drm drm/i915: Serialise updates to GGTT with access through GGTT on Braswell 2015-11-17 17:36:01 +01:00
host1x gpu: host1x: mipi: Power down regulators when unused 2015-08-13 13:47:21 +02:00
ipu-v3 gpu/drm: Kill off set_irq_flags usage 2015-09-16 16:53:38 +02:00
vga vga_switcheroo: Set active attribute to false for audio clients 2015-09-24 20:14:25 +02:00
Makefile