forked from Minki/linux
9b931361ff
Introduce "altr,socfpga-dw-mshc" to enable Altera's SOCFPGA platform specific implementation of the dw_mmc driver. Also add the "syscon" binding to the "altr,sys-mgr" node. The clock driver can use the syscon driver to toggle the register for the SD/MMC clock phase shift settings. Finally, fix an indentation error for the sysmgr node. Signed-off-by: Dinh Nguyen <dinguyen@altera.com> Acked-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Tested-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Chris Ball <chris@printf.net>
70 lines
1.3 KiB
Plaintext
70 lines
1.3 KiB
Plaintext
/*
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* Copyright (C) 2013 Altera Corporation <www.altera.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/dts-v1/;
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/include/ "socfpga.dtsi"
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/ {
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soc {
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clkmgr@ffd04000 {
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clocks {
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osc1 {
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clock-frequency = <25000000>;
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};
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};
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};
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dwmmc0@ff704000 {
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num-slots = <1>;
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supports-highspeed;
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broken-cd;
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slot@0 {
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reg = <0>;
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bus-width = <4>;
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};
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};
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serial0@ffc02000 {
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clock-frequency = <100000000>;
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};
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serial1@ffc03000 {
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clock-frequency = <100000000>;
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};
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sysmgr@ffd08000 {
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cpu1-start-addr = <0xffd080c4>;
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};
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timer0@ffc08000 {
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clock-frequency = <100000000>;
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};
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timer1@ffc09000 {
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clock-frequency = <100000000>;
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};
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timer2@ffd00000 {
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clock-frequency = <25000000>;
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};
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timer3@ffd01000 {
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clock-frequency = <25000000>;
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};
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};
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};
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