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linux/Documentation/devicetree/bindings/arm/altera
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Thor Thayer d31e2e846b ARM: dts: Add Altera L2 Cache and OCRAM EDAC entries 
Add the device tree entries and bindings needed to support the Altera L2
cache and On-Chip RAM EDAC. This patch relies upon an earlier patch to
declare and setup On-chip RAM properly:

  8b907c8b62 ("arm: dts: socfpga: Add OCRAM node")

Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
Acked-by: Rob Herring <robh@kernel.org>
Cc: devicetree@vger.kernel.org
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: galak@codeaurora.org
Cc: grant.likely@linaro.org
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: ijc+devicetree@hellion.org.uk
Cc: Kumar Gala <galak@codeaurora.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux@arm.linux.org.uk
Cc: linux-doc@vger.kernel.org
Cc: linux-edac <linux-edac@vger.kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: m.chehab@samsung.com
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Russell King <linux@arm.linux.org.uk>
Link: http://lkml.kernel.org/r/1455132384-17108-2-git-send-email-tthayer@opensource.altera.com
Signed-off-by: Borislav Petkov <bp@suse.de>
2016-02-11 12:29:38 +01:00
..
socfpga-clk-manager.txt
socfpga-eccmgr.txt ARM: dts: Add Altera L2 Cache and OCRAM EDAC entries 2016-02-11 12:29:38 +01:00
socfpga-sdram-controller.txt ARM: socfpga: dts: add sdram controller dt binding doc 2015-06-02 14:19:27 -05:00
socfpga-sdram-edac.txt arm: socfpga: dts: Add Arria10 SDRAM EDAC DTS support 2015-06-24 18:16:10 +02:00
socfpga-system.txt