forked from Minki/linux
5a2a7d57ee
Currently, all pinctrl setting nodes are defined in <soc>.dtsi, so that boards that share the same pinctrl setting do not have to define it time and time again in <board>.dts. However, along with the devices and use cases being added continuously, the pinctrl setting nodes under iomuxc becomes more than expected. This bloats device tree blob for particular board unnecessarily since only a small subset of those pinctrl setting nodes will be used by the board. It impacts not only the DTB file size but also the run-time device tree lookup efficiency. The patch moves all the pinctrl data into individual boards as needed. With the changes, the pinctrl setting nodes becomes local to particular board, and it makes no sense to continue numbering the setting for given peripheral. Thus, all the pinctrl phandler name gets updated to have only peripheral name in there. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
201 lines
4.8 KiB
Plaintext
201 lines
4.8 KiB
Plaintext
/*
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* Copyright 2013 Armadeus Systems - <support@armadeus.com>
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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/* APF51Dev is a docking board for the APF51 SOM */
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#include "imx51-apf51.dts"
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/ {
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model = "Armadeus Systems APF51Dev docking/development board";
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compatible = "armadeus,imx51-apf51dev", "armadeus,imx51-apf51", "fsl,imx51";
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display@di1 {
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compatible = "fsl,imx-parallel-display";
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crtcs = <&ipu 0>;
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interface-pix-fmt = "bgr666";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ipu_disp1>;
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display-timings {
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lw700 {
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native-mode;
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clock-frequency = <33000033>;
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hactive = <800>;
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vactive = <480>;
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hback-porch = <96>;
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hfront-porch = <96>;
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vback-porch = <20>;
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vfront-porch = <21>;
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hsync-len = <64>;
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vsync-len = <4>;
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hsync-active = <1>;
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vsync-active = <1>;
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de-active = <1>;
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pixelclk-active = <0>;
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};
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};
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};
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gpio-keys {
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compatible = "gpio-keys";
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user-key {
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label = "user";
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gpios = <&gpio1 3 0>;
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linux,code = <256>; /* BTN_0 */
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};
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};
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leds {
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compatible = "gpio-leds";
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user {
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label = "Heartbeat";
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gpios = <&gpio1 2 0>;
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linux,default-trigger = "heartbeat";
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};
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};
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};
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&ecspi1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ecspi1>;
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fsl,spi-num-chipselects = <2>;
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cs-gpios = <&gpio4 24 0>, <&gpio4 25 0>;
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status = "okay";
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};
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&ecspi2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ecspi2>;
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fsl,spi-num-chipselects = <2>;
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cs-gpios = <&gpio3 28 1>, <&gpio3 27 1>;
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status = "okay";
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};
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&esdhc1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_esdhc1>;
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cd-gpios = <&gpio2 29 0>;
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bus-width = <4>;
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status = "okay";
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};
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&esdhc2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_esdhc2>;
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bus-width = <4>;
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non-removable;
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status = "okay";
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};
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&i2c2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c2>;
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status = "okay";
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};
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&iomuxc {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_hog>;
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imx51-apf51dev {
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pinctrl_hog: hoggrp {
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fsl,pins = <
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MX51_PAD_EIM_EB2__GPIO2_22 0x0C5
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MX51_PAD_EIM_EB3__GPIO2_23 0x0C5
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MX51_PAD_EIM_CS4__GPIO2_29 0x100
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MX51_PAD_NANDF_D13__GPIO3_27 0x0C5
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MX51_PAD_NANDF_D12__GPIO3_28 0x0C5
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MX51_PAD_CSPI1_SS0__GPIO4_24 0x0C5
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MX51_PAD_CSPI1_SS1__GPIO4_25 0x0C5
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MX51_PAD_GPIO1_2__GPIO1_2 0x0C5
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MX51_PAD_GPIO1_3__GPIO1_3 0x0C5
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>;
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};
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pinctrl_ecspi1: ecspi1grp {
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fsl,pins = <
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MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185
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MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185
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MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185
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>;
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};
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pinctrl_ecspi2: ecspi2grp {
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fsl,pins = <
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MX51_PAD_NANDF_RB3__ECSPI2_MISO 0x185
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MX51_PAD_NANDF_D15__ECSPI2_MOSI 0x185
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MX51_PAD_NANDF_RB2__ECSPI2_SCLK 0x185
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>;
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};
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pinctrl_esdhc1: esdhc1grp {
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fsl,pins = <
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MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5
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MX51_PAD_SD1_CLK__SD1_CLK 0x20d5
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MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5
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MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5
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MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5
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MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5
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>;
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};
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pinctrl_esdhc2: esdhc2grp {
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fsl,pins = <
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MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5
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MX51_PAD_SD2_CLK__SD2_CLK 0x20d5
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MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5
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MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5
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MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5
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MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5
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>;
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};
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pinctrl_i2c2: i2c2grp {
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fsl,pins = <
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MX51_PAD_EIM_D27__I2C2_SCL 0x400001ed
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MX51_PAD_EIM_D24__I2C2_SDA 0x400001ed
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>;
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};
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pinctrl_ipu_disp1: ipudisp1grp {
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fsl,pins = <
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MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5
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MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5
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MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5
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MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5
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MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5
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MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5
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MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5
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MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5
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MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5
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MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5
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MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5
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MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5
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MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5
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MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5
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MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5
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MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5
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MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5
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MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5
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MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5
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MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5
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MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5
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MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5
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MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5
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MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5
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MX51_PAD_DI1_PIN2__DI1_PIN2 0x5
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MX51_PAD_DI1_PIN3__DI1_PIN3 0x5
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>;
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};
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};
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};
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