forked from Minki/linux
896ad420db
Interrupt DMA11 is the shared interrupt for DMA channels 11 to 14 Interrupt DMA12 is the shared interrupt triggering for any DMA channel (this also includes DMA channel 15) Signed-off-by: Martin Sperl <kernel@martin.sperl.org> Reviewed-by: Eric Anholt <eric@anholt.net> Acked-by: Rob Herring <robh@kernel.org>
134 lines
2.8 KiB
Plaintext
134 lines
2.8 KiB
Plaintext
BCM2835 Top-Level ("ARMCTRL") Interrupt Controller
|
|
|
|
The BCM2835 contains a custom top-level interrupt controller, which supports
|
|
72 interrupt sources using a 2-level register scheme. The interrupt
|
|
controller, or the HW block containing it, is referred to occasionally
|
|
as "armctrl" in the SoC documentation, hence naming of this binding.
|
|
|
|
The BCM2836 contains the same interrupt controller with the same
|
|
interrupts, but the per-CPU interrupt controller is the root, and an
|
|
interrupt there indicates that the ARMCTRL has an interrupt to handle.
|
|
|
|
Required properties:
|
|
|
|
- compatible : should be "brcm,bcm2835-armctrl-ic" or
|
|
"brcm,bcm2836-armctrl-ic"
|
|
- reg : Specifies base physical address and size of the registers.
|
|
- interrupt-controller : Identifies the node as an interrupt controller
|
|
- #interrupt-cells : Specifies the number of cells needed to encode an
|
|
interrupt source. The value shall be 2.
|
|
|
|
The 1st cell is the interrupt bank; 0 for interrupts in the "IRQ basic
|
|
pending" register, or 1/2 respectively for interrupts in the "IRQ pending
|
|
1/2" register.
|
|
|
|
The 2nd cell contains the interrupt number within the bank. Valid values
|
|
are 0..7 for bank 0, and 0..31 for bank 1.
|
|
|
|
Additional required properties for brcm,bcm2836-armctrl-ic:
|
|
- interrupt-parent : Specifies the parent interrupt controller when this
|
|
controller is the second level.
|
|
- interrupts : Specifies the interrupt on the parent for this interrupt
|
|
controller to handle.
|
|
|
|
The interrupt sources are as follows:
|
|
|
|
Bank 0:
|
|
0: ARM_TIMER
|
|
1: ARM_MAILBOX
|
|
2: ARM_DOORBELL_0
|
|
3: ARM_DOORBELL_1
|
|
4: VPU0_HALTED
|
|
5: VPU1_HALTED
|
|
6: ILLEGAL_TYPE0
|
|
7: ILLEGAL_TYPE1
|
|
|
|
Bank 1:
|
|
0: TIMER0
|
|
1: TIMER1
|
|
2: TIMER2
|
|
3: TIMER3
|
|
4: CODEC0
|
|
5: CODEC1
|
|
6: CODEC2
|
|
7: VC_JPEG
|
|
8: ISP
|
|
9: VC_USB
|
|
10: VC_3D
|
|
11: TRANSPOSER
|
|
12: MULTICORESYNC0
|
|
13: MULTICORESYNC1
|
|
14: MULTICORESYNC2
|
|
15: MULTICORESYNC3
|
|
16: DMA0
|
|
17: DMA1
|
|
18: VC_DMA2
|
|
19: VC_DMA3
|
|
20: DMA4
|
|
21: DMA5
|
|
22: DMA6
|
|
23: DMA7
|
|
24: DMA8
|
|
25: DMA9
|
|
26: DMA10
|
|
27: DMA11-14 - shared interrupt for DMA 11 to 14
|
|
28: DMAALL - triggers on all dma interrupts (including chanel 15)
|
|
29: AUX
|
|
30: ARM
|
|
31: VPUDMA
|
|
|
|
Bank 2:
|
|
0: HOSTPORT
|
|
1: VIDEOSCALER
|
|
2: CCP2TX
|
|
3: SDC
|
|
4: DSI0
|
|
5: AVE
|
|
6: CAM0
|
|
7: CAM1
|
|
8: HDMI0
|
|
9: HDMI1
|
|
10: PIXELVALVE1
|
|
11: I2CSPISLV
|
|
12: DSI1
|
|
13: PWA0
|
|
14: PWA1
|
|
15: CPR
|
|
16: SMI
|
|
17: GPIO0
|
|
18: GPIO1
|
|
19: GPIO2
|
|
20: GPIO3
|
|
21: VC_I2C
|
|
22: VC_SPI
|
|
23: VC_I2SPCM
|
|
24: VC_SDIO
|
|
25: VC_UART
|
|
26: SLIMBUS
|
|
27: VEC
|
|
28: CPG
|
|
29: RNG
|
|
30: VC_ARASANSDIO
|
|
31: AVSPMON
|
|
|
|
Example:
|
|
|
|
/* BCM2835, first level */
|
|
intc: interrupt-controller {
|
|
compatible = "brcm,bcm2835-armctrl-ic";
|
|
reg = <0x7e00b200 0x200>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
/* BCM2836, second level */
|
|
intc: interrupt-controller {
|
|
compatible = "brcm,bcm2836-armctrl-ic";
|
|
reg = <0x7e00b200 0x200>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
|
|
interrupt-parent = <&local_intc>;
|
|
interrupts = <8>;
|
|
};
|