3a5a4366ce
Luis reports that, when reverse debugging with GDB, single-step does not function as expected on arm64: | I've noticed, under very specific conditions, that a PTRACE_SINGLESTEP | request by GDB won't execute the underlying instruction. As a consequence, | the PC doesn't move, but we return a SIGTRAP just like we would for a | regular successful PTRACE_SINGLESTEP request. The underlying problem is that when the CPU register state is restored as part of a reverse step, the SPSR.SS bit is cleared and so the hardware single-step state can transition to the "active-pending" state, causing an unexpected step exception to be taken immediately if a step operation is attempted. In hindsight, we probably shouldn't have exposed SPSR.SS in the pstate accessible by the GPR regset, but it's a bit late for that now. Instead, simply prevent userspace from configuring the bit to a value which is inconsistent with the TIF_SINGLESTEP state for the task being traced. Cc: <stable@vger.kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Keno Fischer <keno@juliacomputing.com> Link: https://lore.kernel.org/r/1eed6d69-d53d-9657-1fc9-c089be07f98c@linaro.org Reported-by: Luis Machado <luis.machado@linaro.org> Tested-by: Luis Machado <luis.machado@linaro.org> Signed-off-by: Will Deacon <will@kernel.org>
134 lines
3.4 KiB
C
134 lines
3.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2012 ARM Ltd.
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*/
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#ifndef __ASM_DEBUG_MONITORS_H
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#define __ASM_DEBUG_MONITORS_H
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#include <linux/errno.h>
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#include <linux/types.h>
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#include <asm/brk-imm.h>
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#include <asm/esr.h>
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#include <asm/insn.h>
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#include <asm/ptrace.h>
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/* Low-level stepping controls. */
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#define DBG_MDSCR_SS (1 << 0)
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#define DBG_SPSR_SS (1 << 21)
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/* MDSCR_EL1 enabling bits */
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#define DBG_MDSCR_KDE (1 << 13)
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#define DBG_MDSCR_MDE (1 << 15)
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#define DBG_MDSCR_MASK ~(DBG_MDSCR_KDE | DBG_MDSCR_MDE)
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#define DBG_ESR_EVT(x) (((x) >> 27) & 0x7)
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/* AArch64 */
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#define DBG_ESR_EVT_HWBP 0x0
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#define DBG_ESR_EVT_HWSS 0x1
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#define DBG_ESR_EVT_HWWP 0x2
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#define DBG_ESR_EVT_BRK 0x6
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/*
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* Break point instruction encoding
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*/
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#define BREAK_INSTR_SIZE AARCH64_INSN_SIZE
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/*
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* BRK instruction encoding
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* The #imm16 value should be placed at bits[20:5] within BRK ins
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*/
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#define AARCH64_BREAK_MON 0xd4200000
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/*
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* BRK instruction for provoking a fault on purpose
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* Unlike kgdb, #imm16 value with unallocated handler is used for faulting.
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*/
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#define AARCH64_BREAK_FAULT (AARCH64_BREAK_MON | (FAULT_BRK_IMM << 5))
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#define AARCH64_BREAK_KGDB_DYN_DBG \
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(AARCH64_BREAK_MON | (KGDB_DYN_DBG_BRK_IMM << 5))
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#define CACHE_FLUSH_IS_SAFE 1
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/* kprobes BRK opcodes with ESR encoding */
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#define BRK64_OPCODE_KPROBES (AARCH64_BREAK_MON | (KPROBES_BRK_IMM << 5))
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/* uprobes BRK opcodes with ESR encoding */
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#define BRK64_OPCODE_UPROBES (AARCH64_BREAK_MON | (UPROBES_BRK_IMM << 5))
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/* AArch32 */
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#define DBG_ESR_EVT_BKPT 0x4
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#define DBG_ESR_EVT_VECC 0x5
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#define AARCH32_BREAK_ARM 0x07f001f0
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#define AARCH32_BREAK_THUMB 0xde01
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#define AARCH32_BREAK_THUMB2_LO 0xf7f0
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#define AARCH32_BREAK_THUMB2_HI 0xa000
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#ifndef __ASSEMBLY__
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struct task_struct;
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#define DBG_ARCH_ID_RESERVED 0 /* In case of ptrace ABI updates. */
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#define DBG_HOOK_HANDLED 0
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#define DBG_HOOK_ERROR 1
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struct step_hook {
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struct list_head node;
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int (*fn)(struct pt_regs *regs, unsigned int esr);
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};
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void register_user_step_hook(struct step_hook *hook);
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void unregister_user_step_hook(struct step_hook *hook);
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void register_kernel_step_hook(struct step_hook *hook);
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void unregister_kernel_step_hook(struct step_hook *hook);
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struct break_hook {
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struct list_head node;
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int (*fn)(struct pt_regs *regs, unsigned int esr);
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u16 imm;
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u16 mask; /* These bits are ignored when comparing with imm */
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};
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void register_user_break_hook(struct break_hook *hook);
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void unregister_user_break_hook(struct break_hook *hook);
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void register_kernel_break_hook(struct break_hook *hook);
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void unregister_kernel_break_hook(struct break_hook *hook);
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u8 debug_monitors_arch(void);
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enum dbg_active_el {
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DBG_ACTIVE_EL0 = 0,
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DBG_ACTIVE_EL1,
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};
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void enable_debug_monitors(enum dbg_active_el el);
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void disable_debug_monitors(enum dbg_active_el el);
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void user_rewind_single_step(struct task_struct *task);
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void user_fastforward_single_step(struct task_struct *task);
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void user_regs_reset_single_step(struct user_pt_regs *regs,
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struct task_struct *task);
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void kernel_enable_single_step(struct pt_regs *regs);
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void kernel_disable_single_step(void);
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int kernel_active_single_step(void);
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#ifdef CONFIG_HAVE_HW_BREAKPOINT
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int reinstall_suspended_bps(struct pt_regs *regs);
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#else
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static inline int reinstall_suspended_bps(struct pt_regs *regs)
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{
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return -ENODEV;
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}
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#endif
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int aarch32_break_handler(struct pt_regs *regs);
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void debug_traps_init(void);
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#endif /* __ASSEMBLY */
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#endif /* __ASM_DEBUG_MONITORS_H */
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