forked from Minki/linux
0859ed3db9
Implement clock and power gating support for tonga. On Tonga this is handles by the SMU rather than direct register settings in the driver. Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
351 lines
9.3 KiB
C
351 lines
9.3 KiB
C
/*
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* Copyright 2015 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "hwmgr.h"
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#include "tonga_clockpowergating.h"
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#include "tonga_ppsmc.h"
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#include "tonga_hwmgr.h"
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int tonga_phm_powerdown_uvd(struct pp_hwmgr *hwmgr)
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{
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if (phm_cf_want_uvd_power_gating(hwmgr))
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return smum_send_msg_to_smc(hwmgr->smumgr,
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PPSMC_MSG_UVDPowerOFF);
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return 0;
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}
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int tonga_phm_powerup_uvd(struct pp_hwmgr *hwmgr)
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{
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if (phm_cf_want_uvd_power_gating(hwmgr)) {
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if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
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PHM_PlatformCaps_UVDDynamicPowerGating)) {
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return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
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PPSMC_MSG_UVDPowerON, 1);
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} else {
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return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
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PPSMC_MSG_UVDPowerON, 0);
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}
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}
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return 0;
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}
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int tonga_phm_powerdown_vce(struct pp_hwmgr *hwmgr)
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{
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if (phm_cf_want_vce_power_gating(hwmgr))
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return smum_send_msg_to_smc(hwmgr->smumgr,
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PPSMC_MSG_VCEPowerOFF);
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return 0;
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}
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int tonga_phm_powerup_vce(struct pp_hwmgr *hwmgr)
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{
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if (phm_cf_want_vce_power_gating(hwmgr))
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return smum_send_msg_to_smc(hwmgr->smumgr,
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PPSMC_MSG_VCEPowerON);
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return 0;
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}
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int tonga_phm_set_asic_block_gating(struct pp_hwmgr *hwmgr, enum PHM_AsicBlock block, enum PHM_ClockGateSetting gating)
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{
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int ret = 0;
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switch (block) {
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case PHM_AsicBlock_UVD_MVC:
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case PHM_AsicBlock_UVD:
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case PHM_AsicBlock_UVD_HD:
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case PHM_AsicBlock_UVD_SD:
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if (gating == PHM_ClockGateSetting_StaticOff)
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ret = tonga_phm_powerdown_uvd(hwmgr);
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else
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ret = tonga_phm_powerup_uvd(hwmgr);
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break;
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case PHM_AsicBlock_GFX:
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default:
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break;
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}
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return ret;
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}
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int tonga_phm_disable_clock_power_gating(struct pp_hwmgr *hwmgr)
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{
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struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
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data->uvd_power_gated = false;
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data->vce_power_gated = false;
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tonga_phm_powerup_uvd(hwmgr);
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tonga_phm_powerup_vce(hwmgr);
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return 0;
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}
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int tonga_phm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
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{
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struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
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if (data->uvd_power_gated == bgate)
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return 0;
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data->uvd_power_gated = bgate;
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if (bgate) {
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cgs_set_clockgating_state(hwmgr->device,
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AMD_IP_BLOCK_TYPE_UVD,
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AMD_CG_STATE_UNGATE);
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cgs_set_powergating_state(hwmgr->device,
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AMD_IP_BLOCK_TYPE_UVD,
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AMD_PG_STATE_GATE);
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tonga_update_uvd_dpm(hwmgr, true);
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tonga_phm_powerdown_uvd(hwmgr);
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} else {
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tonga_phm_powerup_uvd(hwmgr);
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cgs_set_powergating_state(hwmgr->device,
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AMD_IP_BLOCK_TYPE_UVD,
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AMD_PG_STATE_UNGATE);
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cgs_set_clockgating_state(hwmgr->device,
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AMD_IP_BLOCK_TYPE_UVD,
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AMD_PG_STATE_GATE);
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tonga_update_uvd_dpm(hwmgr, false);
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}
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return 0;
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}
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int tonga_phm_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate)
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{
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struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
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struct phm_set_power_state_input states;
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const struct pp_power_state *pcurrent;
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struct pp_power_state *requested;
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pcurrent = hwmgr->current_ps;
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requested = hwmgr->request_ps;
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states.pcurrent_state = &(pcurrent->hardware);
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states.pnew_state = &(requested->hardware);
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if (phm_cf_want_vce_power_gating(hwmgr)) {
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if (data->vce_power_gated != bgate) {
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if (bgate) {
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cgs_set_clockgating_state(
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hwmgr->device,
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AMD_IP_BLOCK_TYPE_VCE,
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AMD_CG_STATE_UNGATE);
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cgs_set_powergating_state(
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hwmgr->device,
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AMD_IP_BLOCK_TYPE_VCE,
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AMD_PG_STATE_GATE);
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tonga_enable_disable_vce_dpm(hwmgr, false);
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data->vce_power_gated = true;
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} else {
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tonga_phm_powerup_vce(hwmgr);
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data->vce_power_gated = false;
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cgs_set_powergating_state(
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hwmgr->device,
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AMD_IP_BLOCK_TYPE_VCE,
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AMD_PG_STATE_UNGATE);
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cgs_set_clockgating_state(
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hwmgr->device,
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AMD_IP_BLOCK_TYPE_VCE,
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AMD_PG_STATE_GATE);
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tonga_update_vce_dpm(hwmgr, &states);
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tonga_enable_disable_vce_dpm(hwmgr, true);
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return 0;
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}
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}
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} else {
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tonga_update_vce_dpm(hwmgr, &states);
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tonga_enable_disable_vce_dpm(hwmgr, true);
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return 0;
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}
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if (!data->vce_power_gated)
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tonga_update_vce_dpm(hwmgr, &states);
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return 0;
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}
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int tonga_phm_update_clock_gatings(struct pp_hwmgr *hwmgr,
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const uint32_t *msg_id)
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{
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PPSMC_Msg msg;
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uint32_t value;
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switch ((*msg_id & PP_GROUP_MASK) >> PP_GROUP_SHIFT) {
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case PP_GROUP_GFX:
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switch ((*msg_id & PP_BLOCK_MASK) >> PP_BLOCK_SHIFT) {
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case PP_BLOCK_GFX_CG:
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if (PP_STATE_SUPPORT_CG & *msg_id) {
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msg = ((*msg_id & PP_STATE_MASK) & PP_STATE_CG)
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? PPSMC_MSG_EnableClockGatingFeature
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: PPSMC_MSG_DisableClockGatingFeature;
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value = CG_GFX_CGCG_MASK;
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if (0 != smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, msg, value))
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return -1;
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}
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if (PP_STATE_SUPPORT_LS & *msg_id) {
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msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS
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? PPSMC_MSG_EnableClockGatingFeature
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: PPSMC_MSG_DisableClockGatingFeature;
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value = CG_GFX_CGLS_MASK;
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if (0 != smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, msg, value))
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return -1;
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}
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break;
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case PP_BLOCK_GFX_MG:
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/* For GFX MGCG, there are three different ones;
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* CPF, RLC, and all others. CPF MGCG will not be used for Tonga.
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* For GFX MGLS, Tonga will not support it.
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* */
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if (PP_STATE_SUPPORT_CG & *msg_id) {
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msg = ((*msg_id & PP_STATE_MASK) & PP_STATE_CG)
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? PPSMC_MSG_EnableClockGatingFeature
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: PPSMC_MSG_DisableClockGatingFeature;
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value = (CG_RLC_MGCG_MASK | CG_GFX_OTHERS_MGCG_MASK);
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if (0 != smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, msg, value))
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return -1;
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}
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break;
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default:
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return -1;
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}
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break;
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case PP_GROUP_SYS:
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switch ((*msg_id & PP_BLOCK_MASK) >> PP_BLOCK_SHIFT) {
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case PP_BLOCK_SYS_BIF:
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if (PP_STATE_SUPPORT_LS & *msg_id) {
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msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS
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? PPSMC_MSG_EnableClockGatingFeature
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: PPSMC_MSG_DisableClockGatingFeature;
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value = CG_SYS_BIF_MGLS_MASK;
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if (0 != smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, msg, value))
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return -1;
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}
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break;
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case PP_BLOCK_SYS_MC:
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if (PP_STATE_SUPPORT_CG & *msg_id) {
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msg = ((*msg_id & PP_STATE_MASK) & PP_STATE_CG)
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? PPSMC_MSG_EnableClockGatingFeature
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: PPSMC_MSG_DisableClockGatingFeature;
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value = CG_SYS_MC_MGCG_MASK;
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if (0 != smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, msg, value))
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return -1;
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}
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if (PP_STATE_SUPPORT_LS & *msg_id) {
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msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS
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? PPSMC_MSG_EnableClockGatingFeature
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: PPSMC_MSG_DisableClockGatingFeature;
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value = CG_SYS_MC_MGLS_MASK;
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if (0 != smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, msg, value))
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return -1;
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}
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break;
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case PP_BLOCK_SYS_HDP:
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if (PP_STATE_SUPPORT_CG & *msg_id) {
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msg = ((*msg_id & PP_STATE_MASK) & PP_STATE_CG)
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? PPSMC_MSG_EnableClockGatingFeature
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: PPSMC_MSG_DisableClockGatingFeature;
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value = CG_SYS_HDP_MGCG_MASK;
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if (0 != smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, msg, value))
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return -1;
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}
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if (PP_STATE_SUPPORT_LS & *msg_id) {
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msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS
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? PPSMC_MSG_EnableClockGatingFeature
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: PPSMC_MSG_DisableClockGatingFeature;
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value = CG_SYS_HDP_MGLS_MASK;
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if (0 != smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, msg, value))
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return -1;
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}
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break;
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case PP_BLOCK_SYS_SDMA:
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if (PP_STATE_SUPPORT_CG & *msg_id) {
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msg = ((*msg_id & PP_STATE_MASK) & PP_STATE_CG)
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? PPSMC_MSG_EnableClockGatingFeature
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: PPSMC_MSG_DisableClockGatingFeature;
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value = CG_SYS_SDMA_MGCG_MASK;
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if (0 != smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, msg, value))
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return -1;
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}
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if (PP_STATE_SUPPORT_LS & *msg_id) {
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msg = (*msg_id & PP_STATE_MASK) & PP_STATE_LS
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? PPSMC_MSG_EnableClockGatingFeature
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: PPSMC_MSG_DisableClockGatingFeature;
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value = CG_SYS_SDMA_MGLS_MASK;
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if (0 != smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, msg, value))
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return -1;
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}
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break;
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case PP_BLOCK_SYS_ROM:
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if (PP_STATE_SUPPORT_CG & *msg_id) {
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msg = ((*msg_id & PP_STATE_MASK) & PP_STATE_CG)
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? PPSMC_MSG_EnableClockGatingFeature
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: PPSMC_MSG_DisableClockGatingFeature;
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value = CG_SYS_ROM_MASK;
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if (0 != smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, msg, value))
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return -1;
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}
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break;
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default:
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return -1;
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}
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break;
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default:
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return -1;
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}
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return 0;
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}
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