forked from Minki/linux
df7701621b
Move the clock-related properties in the DesignWare PCIe controller bindings to 'optional' set of properties. [bhelgaas: move to separate patch] Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
31 lines
1.2 KiB
Plaintext
31 lines
1.2 KiB
Plaintext
* Synopsys Designware PCIe interface
|
|
|
|
Required properties:
|
|
- compatible: should contain "snps,dw-pcie" to identify the core.
|
|
- reg: Should contain the configuration address space.
|
|
- reg-names: Must be "config" for the PCIe configuration space.
|
|
(The old way of getting the configuration address space from "ranges"
|
|
is deprecated and should be avoided.)
|
|
- #address-cells: set to <3>
|
|
- #size-cells: set to <2>
|
|
- device_type: set to "pci"
|
|
- ranges: ranges for the PCI memory and I/O regions
|
|
- #interrupt-cells: set to <1>
|
|
- interrupt-map-mask and interrupt-map: standard PCI properties
|
|
to define the mapping of the PCIe interface to interrupt
|
|
numbers.
|
|
- num-lanes: number of lanes to use
|
|
|
|
Optional properties:
|
|
- num-lanes: number of lanes to use (this property should be specified unless
|
|
the link is brought already up in BIOS)
|
|
- reset-gpio: gpio pin number of power good signal
|
|
- bus-range: PCI bus numbers covered (it is recommended for new devicetrees to
|
|
specify this property, to keep backwards compatibility a range of 0x00-0xff
|
|
is assumed if not present)
|
|
- clocks: Must contain an entry for each entry in clock-names.
|
|
See ../clocks/clock-bindings.txt for details.
|
|
- clock-names: Must include the following entries:
|
|
- "pcie"
|
|
- "pcie_bus"
|