forked from Minki/linux
10c03f6968
Add the glue for ARM11 SMP oprofile support, which also supports the performance monitor in the coherency unit. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
297 lines
6.5 KiB
C
297 lines
6.5 KiB
C
/**
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* @file op_model_mpcore.c
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* MPCORE Event Monitor Driver
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* @remark Copyright 2004 ARM SMP Development Team
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* @remark Copyright 2000-2004 Deepak Saxena <dsaxena@mvista.com>
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* @remark Copyright 2000-2004 MontaVista Software Inc
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* @remark Copyright 2004 Dave Jiang <dave.jiang@intel.com>
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* @remark Copyright 2004 Intel Corporation
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* @remark Copyright 2004 Zwane Mwaikambo <zwane@arm.linux.org.uk>
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* @remark Copyright 2004 Oprofile Authors
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*
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* @remark Read the file COPYING
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*
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* @author Zwane Mwaikambo
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*
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* Counters:
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* 0: PMN0 on CPU0, per-cpu configurable event counter
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* 1: PMN1 on CPU0, per-cpu configurable event counter
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* 2: CCNT on CPU0
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* 3: PMN0 on CPU1
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* 4: PMN1 on CPU1
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* 5: CCNT on CPU1
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* 6: PMN0 on CPU1
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* 7: PMN1 on CPU1
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* 8: CCNT on CPU1
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* 9: PMN0 on CPU1
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* 10: PMN1 on CPU1
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* 11: CCNT on CPU1
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* 12-19: configurable SCU event counters
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*/
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/* #define DEBUG */
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#include <linux/types.h>
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#include <linux/errno.h>
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#include <linux/sched.h>
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#include <linux/oprofile.h>
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#include <linux/interrupt.h>
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#include <linux/smp.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/mach/irq.h>
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#include <asm/hardware.h>
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#include <asm/system.h>
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#include "op_counter.h"
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#include "op_arm_model.h"
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#include "op_model_arm11_core.h"
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#include "op_model_mpcore.h"
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/*
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* MPCore SCU event monitor support
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*/
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#define SCU_EVENTMONITORS_VA_BASE __io_address(REALVIEW_MPCORE_SCU_BASE + 0x10)
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/*
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* Bitmask of used SCU counters
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*/
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static unsigned int scu_em_used;
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/*
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* 2 helper fns take a counter number from 0-7 (not the userspace-visible counter number)
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*/
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static inline void scu_reset_counter(struct eventmonitor __iomem *emc, unsigned int n)
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{
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writel(-(u32)counter_config[SCU_COUNTER(n)].count, &emc->MC[n]);
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}
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static inline void scu_set_event(struct eventmonitor __iomem *emc, unsigned int n, u32 event)
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{
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event &= 0xff;
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writeb(event, &emc->MCEB[n]);
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}
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/*
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* SCU counters' IRQ handler (one IRQ per counter => 2 IRQs per CPU)
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*/
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static irqreturn_t scu_em_interrupt(int irq, void *arg)
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{
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struct eventmonitor __iomem *emc = SCU_EVENTMONITORS_VA_BASE;
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unsigned int cnt;
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cnt = irq - IRQ_PMU_SCU0;
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oprofile_add_sample(get_irq_regs(), SCU_COUNTER(cnt));
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scu_reset_counter(emc, cnt);
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/* Clear overflow flag for this counter */
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writel(1 << (cnt + 16), &emc->PMCR);
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return IRQ_HANDLED;
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}
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/* Configure just the SCU counters that the user has requested */
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static void scu_setup(void)
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{
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struct eventmonitor __iomem *emc = SCU_EVENTMONITORS_VA_BASE;
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unsigned int i;
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scu_em_used = 0;
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for (i = 0; i < NUM_SCU_COUNTERS; i++) {
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if (counter_config[SCU_COUNTER(i)].enabled &&
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counter_config[SCU_COUNTER(i)].event) {
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scu_set_event(emc, i, 0); /* disable counter for now */
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scu_em_used |= 1 << i;
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}
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}
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}
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static int scu_start(void)
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{
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struct eventmonitor __iomem *emc = SCU_EVENTMONITORS_VA_BASE;
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unsigned int temp, i;
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unsigned long event;
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int ret = 0;
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/*
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* request the SCU counter interrupts that we need
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*/
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for (i = 0; i < NUM_SCU_COUNTERS; i++) {
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if (scu_em_used & (1 << i)) {
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ret = request_irq(IRQ_PMU_SCU0 + i, scu_em_interrupt, IRQF_DISABLED, "SCU PMU", NULL);
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if (ret) {
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printk(KERN_ERR "oprofile: unable to request IRQ%u for SCU Event Monitor\n",
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IRQ_PMU_SCU0 + i);
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goto err_free_scu;
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}
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}
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}
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/*
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* clear overflow and enable interrupt for all used counters
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*/
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temp = readl(&emc->PMCR);
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for (i = 0; i < NUM_SCU_COUNTERS; i++) {
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if (scu_em_used & (1 << i)) {
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scu_reset_counter(emc, i);
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event = counter_config[SCU_COUNTER(i)].event;
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scu_set_event(emc, i, event);
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/* clear overflow/interrupt */
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temp |= 1 << (i + 16);
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/* enable interrupt*/
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temp |= 1 << (i + 8);
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}
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}
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/* Enable all 8 counters */
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temp |= PMCR_E;
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writel(temp, &emc->PMCR);
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return 0;
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err_free_scu:
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while (i--)
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free_irq(IRQ_PMU_SCU0 + i, NULL);
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return ret;
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}
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static void scu_stop(void)
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{
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struct eventmonitor __iomem *emc = SCU_EVENTMONITORS_VA_BASE;
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unsigned int temp, i;
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/* Disable counter interrupts */
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/* Don't disable all 8 counters (with the E bit) as they may be in use */
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temp = readl(&emc->PMCR);
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for (i = 0; i < NUM_SCU_COUNTERS; i++) {
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if (scu_em_used & (1 << i))
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temp &= ~(1 << (i + 8));
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}
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writel(temp, &emc->PMCR);
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/* Free counter interrupts and reset counters */
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for (i = 0; i < NUM_SCU_COUNTERS; i++) {
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if (scu_em_used & (1 << i)) {
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scu_reset_counter(emc, i);
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free_irq(IRQ_PMU_SCU0 + i, NULL);
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}
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}
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}
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struct em_function_data {
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int (*fn)(void);
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int ret;
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};
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static void em_func(void *data)
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{
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struct em_function_data *d = data;
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int ret = d->fn();
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if (ret)
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d->ret = ret;
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}
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static int em_call_function(int (*fn)(void))
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{
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struct em_function_data data;
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data.fn = fn;
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data.ret = 0;
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smp_call_function(em_func, &data, 1, 1);
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em_func(&data);
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return data.ret;
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}
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/*
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* Glue to stick the individual ARM11 PMUs and the SCU
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* into the oprofile framework.
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*/
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static int em_setup_ctrs(void)
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{
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int ret;
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/* Configure CPU counters by cross-calling to the other CPUs */
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ret = em_call_function(arm11_setup_pmu);
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if (ret == 0)
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scu_setup();
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return 0;
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}
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static int arm11_irqs[] = {
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[0] = IRQ_PMU_CPU0,
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[1] = IRQ_PMU_CPU1,
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[2] = IRQ_PMU_CPU2,
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[3] = IRQ_PMU_CPU3
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};
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static int em_start(void)
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{
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int ret;
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ret = arm11_request_interrupts(arm11_irqs, ARRAY_SIZE(arm11_irqs));
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if (ret == 0) {
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em_call_function(arm11_start_pmu);
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ret = scu_start();
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if (ret)
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arm11_release_interrupts(arm11_irqs, ARRAY_SIZE(arm11_irqs));
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}
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return ret;
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}
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static void em_stop(void)
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{
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em_call_function(arm11_stop_pmu);
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arm11_release_interrupts(arm11_irqs, ARRAY_SIZE(arm11_irqs));
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scu_stop();
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}
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/*
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* Why isn't there a function to route an IRQ to a specific CPU in
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* genirq?
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*/
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static void em_route_irq(int irq, unsigned int cpu)
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{
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irq_desc[irq].affinity = cpumask_of_cpu(cpu);
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irq_desc[irq].chip->set_affinity(irq, cpumask_of_cpu(cpu));
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}
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static int em_setup(void)
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{
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/*
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* Send SCU PMU interrupts to the "owner" CPU.
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*/
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em_route_irq(IRQ_PMU_SCU0, 0);
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em_route_irq(IRQ_PMU_SCU1, 0);
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em_route_irq(IRQ_PMU_SCU2, 1);
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em_route_irq(IRQ_PMU_SCU3, 1);
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em_route_irq(IRQ_PMU_SCU4, 2);
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em_route_irq(IRQ_PMU_SCU5, 2);
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em_route_irq(IRQ_PMU_SCU6, 3);
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em_route_irq(IRQ_PMU_SCU7, 3);
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/*
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* Send CP15 PMU interrupts to the owner CPU.
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*/
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em_route_irq(IRQ_PMU_CPU0, 0);
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em_route_irq(IRQ_PMU_CPU1, 1);
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em_route_irq(IRQ_PMU_CPU2, 2);
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em_route_irq(IRQ_PMU_CPU3, 3);
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return 0;
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}
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struct op_arm_model_spec op_mpcore_spec = {
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.init = em_setup,
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.num_counters = MPCORE_NUM_COUNTERS,
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.setup_ctrs = em_setup_ctrs,
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.start = em_start,
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.stop = em_stop,
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.name = "arm/mpcore",
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};
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