7ed609b002
Switch sama5d3 boards to the new PMC clock bindings. This prevents the wb50n to use the out of spec rate for USART1. Link: https://lore.kernel.org/r/20200110222744.1261464-1-alexandre.belloni@bootlin.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
58 lines
1.5 KiB
Plaintext
58 lines
1.5 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* sama5d3_can.dtsi - Device Tree Include file for SAMA5D3 SoC with
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* CAN support
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*
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* Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
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*/
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#include <dt-bindings/pinctrl/at91.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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/ {
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ahb {
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apb {
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pinctrl@fffff200 {
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can0 {
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pinctrl_can0_rx_tx: can0_rx_tx {
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atmel,pins =
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<AT91_PIOD 14 AT91_PERIPH_C AT91_PINCTRL_NONE /* PD14 periph C RX, conflicts with SCK0, SPI0_NPCS1 */
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AT91_PIOD 15 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PD15 periph C TX, conflicts with CTS0, SPI0_NPCS2 */
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};
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};
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can1 {
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pinctrl_can1_rx_tx: can1_rx_tx {
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atmel,pins =
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<AT91_PIOB 14 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB14 periph B RX, conflicts with GCRS */
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AT91_PIOB 15 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB15 periph B TX, conflicts with GCOL */
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};
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};
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};
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can0: can@f000c000 {
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compatible = "atmel,at91sam9x5-can";
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reg = <0xf000c000 0x300>;
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interrupts = <40 IRQ_TYPE_LEVEL_HIGH 3>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_can0_rx_tx>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 40>;
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clock-names = "can_clk";
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status = "disabled";
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};
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can1: can@f8010000 {
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compatible = "atmel,at91sam9x5-can";
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reg = <0xf8010000 0x300>;
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interrupts = <41 IRQ_TYPE_LEVEL_HIGH 3>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_can1_rx_tx>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 41>;
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clock-names = "can_clk";
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status = "disabled";
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};
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};
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};
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};
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