forked from Minki/linux
85fd6d63bf
This patch moves S3C2410 stuff into mach-s3c24xx/ directory so that we can merge the s3c24 series' directories to the just one mach-s3c24xx/ directory. And this patch is including following. - re-ordered alphabetically by option text at Kconfig and Makefile - removed unused option, MACH_N35 - fixed duplcated option name, S3C2410_DMA to S3C24XX_DMA which is in plat-s3c24xx/ Cc: Ben Dooks <ben-linux@fluff.org> Cc: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
54 lines
1.5 KiB
C
54 lines
1.5 KiB
C
/* arch/arm/mach-s3c2410/include/mach/bast-cpld.h
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*
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* Copyright (c) 2003-2004 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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*
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* BAST - CPLD control constants
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_ARCH_BASTCPLD_H
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#define __ASM_ARCH_BASTCPLD_H
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/* CTRL1 - Audio LR routing */
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#define BAST_CPLD_CTRL1_LRCOFF (0x00)
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#define BAST_CPLD_CTRL1_LRCADC (0x01)
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#define BAST_CPLD_CTRL1_LRCDAC (0x02)
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#define BAST_CPLD_CTRL1_LRCARM (0x03)
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#define BAST_CPLD_CTRL1_LRMASK (0x03)
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/* CTRL2 - NAND WP control, IDE Reset assert/check */
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#define BAST_CPLD_CTRL2_WNAND (0x04)
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#define BAST_CPLD_CTLR2_IDERST (0x08)
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/* CTRL3 - rom write control, CPLD identity */
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#define BAST_CPLD_CTRL3_IDMASK (0x0e)
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#define BAST_CPLD_CTRL3_ROMWEN (0x01)
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/* CTRL4 - 8bit LCD interface control/status */
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#define BAST_CPLD_CTRL4_LLAT (0x01)
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#define BAST_CPLD_CTRL4_LCDRW (0x02)
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#define BAST_CPLD_CTRL4_LCDCMD (0x04)
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#define BAST_CPLD_CTRL4_LCDE2 (0x01)
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/* CTRL5 - DMA routing */
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#define BAST_CPLD_DMA0_PRIIDE (0<<0)
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#define BAST_CPLD_DMA0_SECIDE (1<<0)
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#define BAST_CPLD_DMA0_ISA15 (2<<0)
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#define BAST_CPLD_DMA0_ISA36 (3<<0)
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#define BAST_CPLD_DMA1_PRIIDE (0<<2)
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#define BAST_CPLD_DMA1_SECIDE (1<<2)
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#define BAST_CPLD_DMA1_ISA15 (2<<2)
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#define BAST_CPLD_DMA1_ISA36 (3<<2)
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#endif /* __ASM_ARCH_BASTCPLD_H */
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