Shawn Guo 5790d80176 clk: zte: set CLK_SET_RATE_PARENT for a few zx296718 clocks ... To support VOU VGA display driver with different modes, we need to set flag for a few clocks, so that clk_set_rate() call in VOU driver can get VGA device desired pixel rate. While at it, the divider between pll_vga and clk_vga gets corrected, as it's 1:1 instead of 1:2. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Reviewed-by: Jun Nie <jun.nie@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Michael Turquette <mturquette@baylibre.com>		2017-04-12 18:51:29 +02:00
..
clk-zx296702.c	clk: zte: Remove CLK_IS_ROOT	2016-04-15 16:50:07 -07:00
clk-zx296718.c	clk: zte: set CLK_SET_RATE_PARENT for a few zx296718 clocks	2017-04-12 18:51:29 +02:00
clk.c	clk: zte: add audio clocks for zx296718	2017-01-09 16:06:43 -08:00
clk.h	clk: zte: add audio clocks for zx296718	2017-01-09 16:06:43 -08:00
Makefile	clk: zx: register ZX296718 clocks	2016-09-14 13:50:33 -07:00