f3be1e7b2c
Broadwell microarchitecture supports pseudo-locking. Add support for the L3 cache related performance events of these systems so that the success of pseudo-locking can be measured more accurately on these platforms. Signed-off-by: Reinette Chatre <reinette.chatre@intel.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: fenghua.yu@intel.com Cc: tony.luck@intel.com Cc: vikas.shivappa@linux.intel.com Cc: gavin.hindman@intel.com Cc: jithu.joseph@intel.com Cc: dave.hansen@intel.com Cc: hpa@zytor.com Link: https://lkml.kernel.org/r/36c1414e9bd17c3faf440f32b644b9c879bcbae2.1529706536.git.reinette.chatre@intel.com
44 lines
1.3 KiB
C
44 lines
1.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#undef TRACE_SYSTEM
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#define TRACE_SYSTEM resctrl
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#if !defined(_TRACE_PSEUDO_LOCK_H) || defined(TRACE_HEADER_MULTI_READ)
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#define _TRACE_PSEUDO_LOCK_H
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#include <linux/tracepoint.h>
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TRACE_EVENT(pseudo_lock_mem_latency,
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TP_PROTO(u32 latency),
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TP_ARGS(latency),
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TP_STRUCT__entry(__field(u32, latency)),
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TP_fast_assign(__entry->latency = latency),
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TP_printk("latency=%u", __entry->latency)
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);
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TRACE_EVENT(pseudo_lock_l2,
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TP_PROTO(u64 l2_hits, u64 l2_miss),
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TP_ARGS(l2_hits, l2_miss),
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TP_STRUCT__entry(__field(u64, l2_hits)
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__field(u64, l2_miss)),
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TP_fast_assign(__entry->l2_hits = l2_hits;
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__entry->l2_miss = l2_miss;),
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TP_printk("hits=%llu miss=%llu",
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__entry->l2_hits, __entry->l2_miss));
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TRACE_EVENT(pseudo_lock_l3,
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TP_PROTO(u64 l3_hits, u64 l3_miss),
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TP_ARGS(l3_hits, l3_miss),
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TP_STRUCT__entry(__field(u64, l3_hits)
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__field(u64, l3_miss)),
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TP_fast_assign(__entry->l3_hits = l3_hits;
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__entry->l3_miss = l3_miss;),
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TP_printk("hits=%llu miss=%llu",
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__entry->l3_hits, __entry->l3_miss));
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#endif /* _TRACE_PSEUDO_LOCK_H */
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#undef TRACE_INCLUDE_PATH
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#define TRACE_INCLUDE_PATH .
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#define TRACE_INCLUDE_FILE intel_rdt_pseudo_lock_event
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#include <trace/define_trace.h>
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