forked from Minki/linux
2671618551
Dump a bit more info when the GPU hangs, without having hang_debug enabled (which dumps a *lot* of registers). Also dump the scratch registers, as they are useful for determining where in the cmdstream the GPU hung (and they seem always safe to read when GPU has hung). Note that the freedreno gallium driver emits increasing counter values to SCRATCH6 (to identify tile #) and SCRATCH7 (to identify draw #), so these two in particular can be used to "triangulate" where in the cmdstream the GPU hung. Signed-off-by: Rob Clark <robdclark@gmail.com>
303 lines
8.2 KiB
C
303 lines
8.2 KiB
C
/*
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* Copyright (C) 2013 Red Hat
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* Author: Rob Clark <robdclark@gmail.com>
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*
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* Copyright (c) 2014 The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __ADRENO_GPU_H__
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#define __ADRENO_GPU_H__
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#include <linux/firmware.h>
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#include "msm_gpu.h"
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#include "adreno_common.xml.h"
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#include "adreno_pm4.xml.h"
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#define REG_ADRENO_DEFINE(_offset, _reg) [_offset] = (_reg) + 1
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/**
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* adreno_regs: List of registers that are used in across all
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* 3D devices. Each device type has different offset value for the same
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* register, so an array of register offsets are declared for every device
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* and are indexed by the enumeration values defined in this enum
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*/
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enum adreno_regs {
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REG_ADRENO_CP_DEBUG,
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REG_ADRENO_CP_ME_RAM_WADDR,
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REG_ADRENO_CP_ME_RAM_DATA,
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REG_ADRENO_CP_PFP_UCODE_DATA,
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REG_ADRENO_CP_PFP_UCODE_ADDR,
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REG_ADRENO_CP_WFI_PEND_CTR,
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REG_ADRENO_CP_RB_BASE,
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REG_ADRENO_CP_RB_RPTR_ADDR,
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REG_ADRENO_CP_RB_RPTR,
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REG_ADRENO_CP_RB_WPTR,
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REG_ADRENO_CP_PROTECT_CTRL,
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REG_ADRENO_CP_ME_CNTL,
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REG_ADRENO_CP_RB_CNTL,
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REG_ADRENO_CP_IB1_BASE,
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REG_ADRENO_CP_IB1_BUFSZ,
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REG_ADRENO_CP_IB2_BASE,
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REG_ADRENO_CP_IB2_BUFSZ,
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REG_ADRENO_CP_TIMESTAMP,
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REG_ADRENO_CP_ME_RAM_RADDR,
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REG_ADRENO_CP_ROQ_ADDR,
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REG_ADRENO_CP_ROQ_DATA,
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REG_ADRENO_CP_MERCIU_ADDR,
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REG_ADRENO_CP_MERCIU_DATA,
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REG_ADRENO_CP_MERCIU_DATA2,
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REG_ADRENO_CP_MEQ_ADDR,
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REG_ADRENO_CP_MEQ_DATA,
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REG_ADRENO_CP_HW_FAULT,
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REG_ADRENO_CP_PROTECT_STATUS,
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REG_ADRENO_SCRATCH_ADDR,
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REG_ADRENO_SCRATCH_UMSK,
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REG_ADRENO_SCRATCH_REG2,
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REG_ADRENO_RBBM_STATUS,
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REG_ADRENO_RBBM_PERFCTR_CTL,
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REG_ADRENO_RBBM_PERFCTR_LOAD_CMD0,
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REG_ADRENO_RBBM_PERFCTR_LOAD_CMD1,
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REG_ADRENO_RBBM_PERFCTR_LOAD_CMD2,
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REG_ADRENO_RBBM_PERFCTR_PWR_1_LO,
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REG_ADRENO_RBBM_INT_0_MASK,
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REG_ADRENO_RBBM_INT_0_STATUS,
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REG_ADRENO_RBBM_AHB_ERROR_STATUS,
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REG_ADRENO_RBBM_PM_OVERRIDE2,
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REG_ADRENO_RBBM_AHB_CMD,
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REG_ADRENO_RBBM_INT_CLEAR_CMD,
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REG_ADRENO_RBBM_SW_RESET_CMD,
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REG_ADRENO_RBBM_CLOCK_CTL,
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REG_ADRENO_RBBM_AHB_ME_SPLIT_STATUS,
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REG_ADRENO_RBBM_AHB_PFP_SPLIT_STATUS,
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REG_ADRENO_VPC_DEBUG_RAM_SEL,
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REG_ADRENO_VPC_DEBUG_RAM_READ,
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REG_ADRENO_VSC_SIZE_ADDRESS,
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REG_ADRENO_VFD_CONTROL_0,
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REG_ADRENO_VFD_INDEX_MAX,
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REG_ADRENO_SP_VS_PVT_MEM_ADDR_REG,
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REG_ADRENO_SP_FS_PVT_MEM_ADDR_REG,
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REG_ADRENO_SP_VS_OBJ_START_REG,
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REG_ADRENO_SP_FS_OBJ_START_REG,
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REG_ADRENO_PA_SC_AA_CONFIG,
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REG_ADRENO_SQ_GPR_MANAGEMENT,
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REG_ADRENO_SQ_INST_STORE_MANAGMENT,
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REG_ADRENO_TP0_CHICKEN,
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REG_ADRENO_RBBM_RBBM_CTL,
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REG_ADRENO_UCHE_INVALIDATE0,
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REG_ADRENO_RBBM_PERFCTR_LOAD_VALUE_LO,
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REG_ADRENO_RBBM_PERFCTR_LOAD_VALUE_HI,
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REG_ADRENO_REGISTER_MAX,
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};
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struct adreno_rev {
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uint8_t core;
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uint8_t major;
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uint8_t minor;
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uint8_t patchid;
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};
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#define ADRENO_REV(core, major, minor, patchid) \
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((struct adreno_rev){ core, major, minor, patchid })
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struct adreno_gpu_funcs {
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struct msm_gpu_funcs base;
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};
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struct adreno_info {
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struct adreno_rev rev;
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uint32_t revn;
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const char *name;
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const char *pm4fw, *pfpfw;
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uint32_t gmem;
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struct msm_gpu *(*init)(struct drm_device *dev);
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};
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const struct adreno_info *adreno_info(struct adreno_rev rev);
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struct adreno_rbmemptrs {
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volatile uint32_t rptr;
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volatile uint32_t wptr;
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volatile uint32_t fence;
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};
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struct adreno_gpu {
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struct msm_gpu base;
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struct adreno_rev rev;
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const struct adreno_info *info;
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uint32_t gmem; /* actual gmem size */
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uint32_t revn; /* numeric revision name */
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const struct adreno_gpu_funcs *funcs;
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/* interesting register offsets to dump: */
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const unsigned int *registers;
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/* firmware: */
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const struct firmware *pm4, *pfp;
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/* ringbuffer rptr/wptr: */
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// TODO should this be in msm_ringbuffer? I think it would be
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// different for z180..
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struct adreno_rbmemptrs *memptrs;
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struct drm_gem_object *memptrs_bo;
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uint32_t memptrs_iova;
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/*
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* Register offsets are different between some GPUs.
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* GPU specific offsets will be exported by GPU specific
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* code (a3xx_gpu.c) and stored in this common location.
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*/
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const unsigned int *reg_offsets;
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};
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#define to_adreno_gpu(x) container_of(x, struct adreno_gpu, base)
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/* platform config data (ie. from DT, or pdata) */
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struct adreno_platform_config {
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struct adreno_rev rev;
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uint32_t fast_rate, slow_rate, bus_freq;
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#ifdef CONFIG_MSM_BUS_SCALING
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struct msm_bus_scale_pdata *bus_scale_table;
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#endif
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};
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#define ADRENO_IDLE_TIMEOUT msecs_to_jiffies(1000)
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#define spin_until(X) ({ \
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int __ret = -ETIMEDOUT; \
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unsigned long __t = jiffies + ADRENO_IDLE_TIMEOUT; \
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do { \
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if (X) { \
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__ret = 0; \
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break; \
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} \
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} while (time_before(jiffies, __t)); \
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__ret; \
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})
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static inline bool adreno_is_a3xx(struct adreno_gpu *gpu)
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{
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return (gpu->revn >= 300) && (gpu->revn < 400);
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}
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static inline bool adreno_is_a305(struct adreno_gpu *gpu)
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{
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return gpu->revn == 305;
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}
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static inline bool adreno_is_a320(struct adreno_gpu *gpu)
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{
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return gpu->revn == 320;
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}
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static inline bool adreno_is_a330(struct adreno_gpu *gpu)
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{
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return gpu->revn == 330;
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}
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static inline bool adreno_is_a330v2(struct adreno_gpu *gpu)
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{
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return adreno_is_a330(gpu) && (gpu->rev.patchid > 0);
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}
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static inline bool adreno_is_a4xx(struct adreno_gpu *gpu)
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{
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return (gpu->revn >= 400) && (gpu->revn < 500);
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}
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static inline int adreno_is_a420(struct adreno_gpu *gpu)
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{
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return gpu->revn == 420;
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}
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int adreno_get_param(struct msm_gpu *gpu, uint32_t param, uint64_t *value);
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int adreno_hw_init(struct msm_gpu *gpu);
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uint32_t adreno_last_fence(struct msm_gpu *gpu);
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void adreno_recover(struct msm_gpu *gpu);
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int adreno_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,
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struct msm_file_private *ctx);
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void adreno_flush(struct msm_gpu *gpu);
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void adreno_idle(struct msm_gpu *gpu);
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#ifdef CONFIG_DEBUG_FS
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void adreno_show(struct msm_gpu *gpu, struct seq_file *m);
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#endif
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void adreno_dump_info(struct msm_gpu *gpu);
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void adreno_dump(struct msm_gpu *gpu);
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void adreno_wait_ring(struct msm_gpu *gpu, uint32_t ndwords);
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int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
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struct adreno_gpu *gpu, const struct adreno_gpu_funcs *funcs);
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void adreno_gpu_cleanup(struct adreno_gpu *gpu);
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/* ringbuffer helpers (the parts that are adreno specific) */
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static inline void
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OUT_PKT0(struct msm_ringbuffer *ring, uint16_t regindx, uint16_t cnt)
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{
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adreno_wait_ring(ring->gpu, cnt+1);
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OUT_RING(ring, CP_TYPE0_PKT | ((cnt-1) << 16) | (regindx & 0x7FFF));
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}
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/* no-op packet: */
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static inline void
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OUT_PKT2(struct msm_ringbuffer *ring)
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{
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adreno_wait_ring(ring->gpu, 1);
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OUT_RING(ring, CP_TYPE2_PKT);
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}
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static inline void
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OUT_PKT3(struct msm_ringbuffer *ring, uint8_t opcode, uint16_t cnt)
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{
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adreno_wait_ring(ring->gpu, cnt+1);
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OUT_RING(ring, CP_TYPE3_PKT | ((cnt-1) << 16) | ((opcode & 0xFF) << 8));
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}
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/*
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* adreno_checkreg_off() - Checks the validity of a register enum
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* @gpu: Pointer to struct adreno_gpu
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* @offset_name: The register enum that is checked
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*/
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static inline bool adreno_reg_check(struct adreno_gpu *gpu,
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enum adreno_regs offset_name)
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{
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if (offset_name >= REG_ADRENO_REGISTER_MAX ||
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!gpu->reg_offsets[offset_name]) {
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BUG();
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}
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return true;
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}
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static inline u32 adreno_gpu_read(struct adreno_gpu *gpu,
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enum adreno_regs offset_name)
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{
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u32 reg = gpu->reg_offsets[offset_name];
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u32 val = 0;
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if(adreno_reg_check(gpu,offset_name))
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val = gpu_read(&gpu->base, reg - 1);
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return val;
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}
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static inline void adreno_gpu_write(struct adreno_gpu *gpu,
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enum adreno_regs offset_name, u32 data)
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{
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u32 reg = gpu->reg_offsets[offset_name];
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if(adreno_reg_check(gpu, offset_name))
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gpu_write(&gpu->base, reg - 1, data);
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}
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#endif /* __ADRENO_GPU_H__ */
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