c07cbc1f04
[Why & How] Program modulo with ref dpp clk Mhz/10. Program phase with pipe dpp clk Mhz /10. DMUB FW could use these value to determine optimization clk for PSR power saving. Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Acked-by: Bindu Ramamurthy <bindu.r@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
40 lines
1009 B
Makefile
40 lines
1009 B
Makefile
# SPDX-License-Identifier: MIT
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#
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# Makefile for DCN21.
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DCN21 = dcn21_init.o dcn21_hubp.o dcn21_hubbub.o dcn21_resource.o \
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dcn21_hwseq.o dcn21_link_encoder.o dcn21_dccg.o
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ifdef CONFIG_X86
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CFLAGS_$(AMDDALPATH)/dc/dcn21/dcn21_resource.o := -mhard-float -msse
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endif
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ifdef CONFIG_PPC64
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CFLAGS_$(AMDDALPATH)/dc/dcn21/dcn21_resource.o := -mhard-float -maltivec
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endif
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ifdef CONFIG_ARM64
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CFLAGS_REMOVE_$(AMDDALPATH)/dc/dcn21/dcn21_resource.o := -mgeneral-regs-only
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endif
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ifdef CONFIG_CC_IS_GCC
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ifeq ($(call cc-ifversion, -lt, 0701, y), y)
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IS_OLD_GCC = 1
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endif
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endif
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ifdef CONFIG_X86
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ifdef IS_OLD_GCC
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# Stack alignment mismatch, proceed with caution.
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# GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-boundary=3
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# (8B stack alignment).
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CFLAGS_$(AMDDALPATH)/dc/dcn21/dcn21_resource.o += -mpreferred-stack-boundary=4
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else
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CFLAGS_$(AMDDALPATH)/dc/dcn21/dcn21_resource.o += -msse2
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endif
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endif
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AMD_DAL_DCN21 = $(addprefix $(AMDDALPATH)/dc/dcn21/,$(DCN21))
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AMD_DISPLAY_FILES += $(AMD_DAL_DCN21)
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