forked from Minki/linux
84d89c3123
Add the mailbox device DT node for OMAP5 SoC. The OMAP5 mailbox IP is identical to that used in OMAP4. The OMAP5 hwmod data no longer publishes the module address space, so this patch fixes the WARN_ON backtrace associated with the following trace during the kernel boot: "omap_hwmod: mailbox: doesn't have mpu register target base". Otherwise we get a warning like this: WARNING: CPU: 0 PID: 1 at arch/arm/mach-omap2/omap_hwmod.c:2538 _init+0x1c0/0x3dc() omap_hwmod: mailbox: doesn't have mpu register target base Modules linked in: CPU: 0 PID: 1 Comm: swapper/0 Not tainted 3.15.0-rc2-00001-gb5e85a0 #45 [<c0015724>] (unwind_backtrace) from [<c00120f4>] (show_stack+0x10/0x14) [<c00120f4>] (show_stack) from [<c05a1ccc>] (dump_stack+0x78/0x94) [<c05a1ccc>] (dump_stack) from [<c0042a74>] (warn_slowpath_common+0x6c/0x8c) [<c0042a74>] (warn_slowpath_common) from [<c0042b28>] (warn_slowpath_fmt+0x30/0x40) [<c0042b28>] (warn_slowpath_fmt) from [<c0803b40>] (_init+0x1c0/0x3dc) [<c0803b40>] (_init) from [<c0029c8c>] (omap_hwmod_for_each+0x34/0x5c) [<c0029c8c>] (omap_hwmod_for_each) from [<c08042b0>] (__omap_hwmod_setup_all+0x24/0x40) [<c08042b0>] (__omap_hwmod_setup_all) from [<c00088b8>] (do_one_initcall+0x34/0x160) [<c00088b8>] (do_one_initcall) from [<c07f7bf4>] (kernel_init_freeable+0xfc/0x1c8) [<c07f7bf4>] (kernel_init_freeable) from [<c059c4f4>] (kernel_init+0x8/0xe4) [<c059c4f4>] (kernel_init) from [<c000eaa8>] (ret_from_fork+0x14/0x2c) Signed-off-by: Suman Anna <s-anna@ti.com> [tony@atomide.com: updated description to for the warning] Signed-off-by: Tony Lindgren <tony@atomide.com>
883 lines
21 KiB
Plaintext
883 lines
21 KiB
Plaintext
/*
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* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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* Based on "omap4.dtsi"
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*/
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/pinctrl/omap.h>
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#include "skeleton.dtsi"
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "ti,omap5";
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interrupt-parent = <&gic>;
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aliases {
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i2c0 = &i2c1;
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i2c1 = &i2c2;
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i2c2 = &i2c3;
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i2c3 = &i2c4;
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i2c4 = &i2c5;
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serial0 = &uart1;
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serial1 = &uart2;
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serial2 = &uart3;
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serial3 = &uart4;
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serial4 = &uart5;
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serial5 = &uart6;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0x0>;
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operating-points = <
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/* kHz uV */
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500000 880000
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1000000 1060000
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1500000 1250000
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>;
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clocks = <&dpll_mpu_ck>;
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clock-names = "cpu";
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clock-latency = <300000>; /* From omap-cpufreq driver */
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/* cooling options */
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cooling-min-level = <0>;
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cooling-max-level = <2>;
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#cooling-cells = <2>; /* min followed by max */
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0x1>;
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};
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};
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thermal-zones {
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#include "omap4-cpu-thermal.dtsi"
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#include "omap5-gpu-thermal.dtsi"
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#include "omap5-core-thermal.dtsi"
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};
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timer {
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compatible = "arm,armv7-timer";
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/* PPI secure/nonsecure IRQ */
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>;
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};
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gic: interrupt-controller@48211000 {
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compatible = "arm,cortex-a15-gic";
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interrupt-controller;
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#interrupt-cells = <3>;
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reg = <0x48211000 0x1000>,
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<0x48212000 0x1000>,
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<0x48214000 0x2000>,
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<0x48216000 0x2000>;
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};
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/*
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* The soc node represents the soc top level view. It is used for IPs
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* that are not memory mapped in the MPU view or for the MPU itself.
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*/
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soc {
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compatible = "ti,omap-infra";
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mpu {
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compatible = "ti,omap5-mpu";
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ti,hwmods = "mpu";
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};
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};
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/*
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* XXX: Use a flat representation of the OMAP3 interconnect.
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* The real OMAP interconnect network is quite complex.
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* Since it will not bring real advantage to represent that in DT for
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* the moment, just use a fake OCP bus entry to represent the whole bus
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* hierarchy.
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*/
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ocp {
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compatible = "ti,omap4-l3-noc", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
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reg = <0x44000000 0x2000>,
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<0x44800000 0x3000>,
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<0x45000000 0x4000>;
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interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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prm: prm@4ae06000 {
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compatible = "ti,omap5-prm";
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reg = <0x4ae06000 0x3000>;
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prm_clocks: clocks {
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#address-cells = <1>;
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#size-cells = <0>;
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};
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prm_clockdomains: clockdomains {
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};
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};
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cm_core_aon: cm_core_aon@4a004000 {
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compatible = "ti,omap5-cm-core-aon";
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reg = <0x4a004000 0x2000>;
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cm_core_aon_clocks: clocks {
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#address-cells = <1>;
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#size-cells = <0>;
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};
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cm_core_aon_clockdomains: clockdomains {
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};
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};
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scrm: scrm@4ae0a000 {
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compatible = "ti,omap5-scrm";
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reg = <0x4ae0a000 0x2000>;
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scrm_clocks: clocks {
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#address-cells = <1>;
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#size-cells = <0>;
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};
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scrm_clockdomains: clockdomains {
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};
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};
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cm_core: cm_core@4a008000 {
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compatible = "ti,omap5-cm-core";
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reg = <0x4a008000 0x3000>;
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cm_core_clocks: clocks {
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#address-cells = <1>;
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#size-cells = <0>;
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};
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cm_core_clockdomains: clockdomains {
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};
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};
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counter32k: counter@4ae04000 {
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compatible = "ti,omap-counter32k";
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reg = <0x4ae04000 0x40>;
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ti,hwmods = "counter_32k";
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};
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omap5_pmx_core: pinmux@4a002840 {
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compatible = "ti,omap4-padconf", "pinctrl-single";
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reg = <0x4a002840 0x01b6>;
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-single,register-width = <16>;
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pinctrl-single,function-mask = <0x7fff>;
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};
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omap5_pmx_wkup: pinmux@4ae0c840 {
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compatible = "ti,omap4-padconf", "pinctrl-single";
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reg = <0x4ae0c840 0x0038>;
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-single,register-width = <16>;
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pinctrl-single,function-mask = <0x7fff>;
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};
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omap5_padconf_global: tisyscon@4a002da0 {
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compatible = "syscon";
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reg = <0x4A002da0 0xec>;
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};
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pbias_regulator: pbias_regulator {
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compatible = "ti,pbias-omap";
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reg = <0x60 0x4>;
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syscon = <&omap5_padconf_global>;
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pbias_mmc_reg: pbias_mmc_omap5 {
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regulator-name = "pbias_mmc_omap5";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3000000>;
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};
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};
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sdma: dma-controller@4a056000 {
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compatible = "ti,omap4430-sdma";
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reg = <0x4a056000 0x1000>;
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interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
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#dma-cells = <1>;
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#dma-channels = <32>;
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#dma-requests = <127>;
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};
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gpio1: gpio@4ae10000 {
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compatible = "ti,omap4-gpio";
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reg = <0x4ae10000 0x200>;
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interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
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ti,hwmods = "gpio1";
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ti,gpio-always-on;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio2: gpio@48055000 {
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compatible = "ti,omap4-gpio";
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reg = <0x48055000 0x200>;
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interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
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ti,hwmods = "gpio2";
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio3: gpio@48057000 {
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compatible = "ti,omap4-gpio";
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reg = <0x48057000 0x200>;
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interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
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ti,hwmods = "gpio3";
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio4: gpio@48059000 {
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compatible = "ti,omap4-gpio";
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reg = <0x48059000 0x200>;
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interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
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ti,hwmods = "gpio4";
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio5: gpio@4805b000 {
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compatible = "ti,omap4-gpio";
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reg = <0x4805b000 0x200>;
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interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
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ti,hwmods = "gpio5";
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio6: gpio@4805d000 {
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compatible = "ti,omap4-gpio";
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reg = <0x4805d000 0x200>;
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interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
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ti,hwmods = "gpio6";
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio7: gpio@48051000 {
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compatible = "ti,omap4-gpio";
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reg = <0x48051000 0x200>;
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interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
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ti,hwmods = "gpio7";
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio8: gpio@48053000 {
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compatible = "ti,omap4-gpio";
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reg = <0x48053000 0x200>;
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interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
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ti,hwmods = "gpio8";
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpmc: gpmc@50000000 {
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compatible = "ti,omap4430-gpmc";
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reg = <0x50000000 0x1000>;
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#address-cells = <2>;
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#size-cells = <1>;
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interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
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gpmc,num-cs = <8>;
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gpmc,num-waitpins = <4>;
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ti,hwmods = "gpmc";
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clocks = <&l3_iclk_div>;
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clock-names = "fck";
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};
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i2c1: i2c@48070000 {
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compatible = "ti,omap4-i2c";
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reg = <0x48070000 0x100>;
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interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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ti,hwmods = "i2c1";
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};
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i2c2: i2c@48072000 {
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compatible = "ti,omap4-i2c";
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reg = <0x48072000 0x100>;
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interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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ti,hwmods = "i2c2";
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};
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i2c3: i2c@48060000 {
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compatible = "ti,omap4-i2c";
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reg = <0x48060000 0x100>;
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interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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ti,hwmods = "i2c3";
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};
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i2c4: i2c@4807a000 {
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compatible = "ti,omap4-i2c";
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reg = <0x4807a000 0x100>;
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interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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ti,hwmods = "i2c4";
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};
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i2c5: i2c@4807c000 {
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compatible = "ti,omap4-i2c";
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reg = <0x4807c000 0x100>;
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interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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ti,hwmods = "i2c5";
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};
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hwspinlock: spinlock@4a0f6000 {
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compatible = "ti,omap4-hwspinlock";
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reg = <0x4a0f6000 0x1000>;
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ti,hwmods = "spinlock";
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#hwlock-cells = <1>;
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};
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mcspi1: spi@48098000 {
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compatible = "ti,omap4-mcspi";
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reg = <0x48098000 0x200>;
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interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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ti,hwmods = "mcspi1";
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ti,spi-num-cs = <4>;
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dmas = <&sdma 35>,
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<&sdma 36>,
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<&sdma 37>,
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<&sdma 38>,
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<&sdma 39>,
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<&sdma 40>,
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<&sdma 41>,
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<&sdma 42>;
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dma-names = "tx0", "rx0", "tx1", "rx1",
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"tx2", "rx2", "tx3", "rx3";
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};
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mcspi2: spi@4809a000 {
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compatible = "ti,omap4-mcspi";
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reg = <0x4809a000 0x200>;
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interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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ti,hwmods = "mcspi2";
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ti,spi-num-cs = <2>;
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dmas = <&sdma 43>,
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<&sdma 44>,
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<&sdma 45>,
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<&sdma 46>;
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dma-names = "tx0", "rx0", "tx1", "rx1";
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};
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mcspi3: spi@480b8000 {
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compatible = "ti,omap4-mcspi";
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reg = <0x480b8000 0x200>;
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interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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ti,hwmods = "mcspi3";
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ti,spi-num-cs = <2>;
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dmas = <&sdma 15>, <&sdma 16>;
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dma-names = "tx0", "rx0";
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};
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mcspi4: spi@480ba000 {
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compatible = "ti,omap4-mcspi";
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reg = <0x480ba000 0x200>;
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interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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ti,hwmods = "mcspi4";
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ti,spi-num-cs = <1>;
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dmas = <&sdma 70>, <&sdma 71>;
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dma-names = "tx0", "rx0";
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};
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uart1: serial@4806a000 {
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compatible = "ti,omap4-uart";
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reg = <0x4806a000 0x100>;
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interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
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ti,hwmods = "uart1";
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clock-frequency = <48000000>;
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};
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uart2: serial@4806c000 {
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compatible = "ti,omap4-uart";
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reg = <0x4806c000 0x100>;
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interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
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ti,hwmods = "uart2";
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clock-frequency = <48000000>;
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};
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uart3: serial@48020000 {
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compatible = "ti,omap4-uart";
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|
reg = <0x48020000 0x100>;
|
|
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
|
|
ti,hwmods = "uart3";
|
|
clock-frequency = <48000000>;
|
|
};
|
|
|
|
uart4: serial@4806e000 {
|
|
compatible = "ti,omap4-uart";
|
|
reg = <0x4806e000 0x100>;
|
|
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
|
|
ti,hwmods = "uart4";
|
|
clock-frequency = <48000000>;
|
|
};
|
|
|
|
uart5: serial@48066000 {
|
|
compatible = "ti,omap4-uart";
|
|
reg = <0x48066000 0x100>;
|
|
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
|
|
ti,hwmods = "uart5";
|
|
clock-frequency = <48000000>;
|
|
};
|
|
|
|
uart6: serial@48068000 {
|
|
compatible = "ti,omap4-uart";
|
|
reg = <0x48068000 0x100>;
|
|
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
|
|
ti,hwmods = "uart6";
|
|
clock-frequency = <48000000>;
|
|
};
|
|
|
|
mmc1: mmc@4809c000 {
|
|
compatible = "ti,omap4-hsmmc";
|
|
reg = <0x4809c000 0x400>;
|
|
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
|
|
ti,hwmods = "mmc1";
|
|
ti,dual-volt;
|
|
ti,needs-special-reset;
|
|
dmas = <&sdma 61>, <&sdma 62>;
|
|
dma-names = "tx", "rx";
|
|
pbias-supply = <&pbias_mmc_reg>;
|
|
};
|
|
|
|
mmc2: mmc@480b4000 {
|
|
compatible = "ti,omap4-hsmmc";
|
|
reg = <0x480b4000 0x400>;
|
|
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
|
|
ti,hwmods = "mmc2";
|
|
ti,needs-special-reset;
|
|
dmas = <&sdma 47>, <&sdma 48>;
|
|
dma-names = "tx", "rx";
|
|
};
|
|
|
|
mmc3: mmc@480ad000 {
|
|
compatible = "ti,omap4-hsmmc";
|
|
reg = <0x480ad000 0x400>;
|
|
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
|
|
ti,hwmods = "mmc3";
|
|
ti,needs-special-reset;
|
|
dmas = <&sdma 77>, <&sdma 78>;
|
|
dma-names = "tx", "rx";
|
|
};
|
|
|
|
mmc4: mmc@480d1000 {
|
|
compatible = "ti,omap4-hsmmc";
|
|
reg = <0x480d1000 0x400>;
|
|
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
|
|
ti,hwmods = "mmc4";
|
|
ti,needs-special-reset;
|
|
dmas = <&sdma 57>, <&sdma 58>;
|
|
dma-names = "tx", "rx";
|
|
};
|
|
|
|
mmc5: mmc@480d5000 {
|
|
compatible = "ti,omap4-hsmmc";
|
|
reg = <0x480d5000 0x400>;
|
|
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
|
|
ti,hwmods = "mmc5";
|
|
ti,needs-special-reset;
|
|
dmas = <&sdma 59>, <&sdma 60>;
|
|
dma-names = "tx", "rx";
|
|
};
|
|
|
|
mmu_dsp: mmu@4a066000 {
|
|
compatible = "ti,omap4-iommu";
|
|
reg = <0x4a066000 0x100>;
|
|
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
|
|
ti,hwmods = "mmu_dsp";
|
|
};
|
|
|
|
mmu_ipu: mmu@55082000 {
|
|
compatible = "ti,omap4-iommu";
|
|
reg = <0x55082000 0x100>;
|
|
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
|
|
ti,hwmods = "mmu_ipu";
|
|
ti,iommu-bus-err-back;
|
|
};
|
|
|
|
keypad: keypad@4ae1c000 {
|
|
compatible = "ti,omap4-keypad";
|
|
reg = <0x4ae1c000 0x400>;
|
|
ti,hwmods = "kbd";
|
|
};
|
|
|
|
mcpdm: mcpdm@40132000 {
|
|
compatible = "ti,omap4-mcpdm";
|
|
reg = <0x40132000 0x7f>, /* MPU private access */
|
|
<0x49032000 0x7f>; /* L3 Interconnect */
|
|
reg-names = "mpu", "dma";
|
|
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
|
|
ti,hwmods = "mcpdm";
|
|
dmas = <&sdma 65>,
|
|
<&sdma 66>;
|
|
dma-names = "up_link", "dn_link";
|
|
status = "disabled";
|
|
};
|
|
|
|
dmic: dmic@4012e000 {
|
|
compatible = "ti,omap4-dmic";
|
|
reg = <0x4012e000 0x7f>, /* MPU private access */
|
|
<0x4902e000 0x7f>; /* L3 Interconnect */
|
|
reg-names = "mpu", "dma";
|
|
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
|
|
ti,hwmods = "dmic";
|
|
dmas = <&sdma 67>;
|
|
dma-names = "up_link";
|
|
status = "disabled";
|
|
};
|
|
|
|
mcbsp1: mcbsp@40122000 {
|
|
compatible = "ti,omap4-mcbsp";
|
|
reg = <0x40122000 0xff>, /* MPU private access */
|
|
<0x49022000 0xff>; /* L3 Interconnect */
|
|
reg-names = "mpu", "dma";
|
|
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "common";
|
|
ti,buffer-size = <128>;
|
|
ti,hwmods = "mcbsp1";
|
|
dmas = <&sdma 33>,
|
|
<&sdma 34>;
|
|
dma-names = "tx", "rx";
|
|
status = "disabled";
|
|
};
|
|
|
|
mcbsp2: mcbsp@40124000 {
|
|
compatible = "ti,omap4-mcbsp";
|
|
reg = <0x40124000 0xff>, /* MPU private access */
|
|
<0x49024000 0xff>; /* L3 Interconnect */
|
|
reg-names = "mpu", "dma";
|
|
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "common";
|
|
ti,buffer-size = <128>;
|
|
ti,hwmods = "mcbsp2";
|
|
dmas = <&sdma 17>,
|
|
<&sdma 18>;
|
|
dma-names = "tx", "rx";
|
|
status = "disabled";
|
|
};
|
|
|
|
mcbsp3: mcbsp@40126000 {
|
|
compatible = "ti,omap4-mcbsp";
|
|
reg = <0x40126000 0xff>, /* MPU private access */
|
|
<0x49026000 0xff>; /* L3 Interconnect */
|
|
reg-names = "mpu", "dma";
|
|
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "common";
|
|
ti,buffer-size = <128>;
|
|
ti,hwmods = "mcbsp3";
|
|
dmas = <&sdma 19>,
|
|
<&sdma 20>;
|
|
dma-names = "tx", "rx";
|
|
status = "disabled";
|
|
};
|
|
|
|
mailbox: mailbox@4a0f4000 {
|
|
compatible = "ti,omap4-mailbox";
|
|
reg = <0x4a0f4000 0x200>;
|
|
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
|
|
ti,hwmods = "mailbox";
|
|
};
|
|
|
|
timer1: timer@4ae18000 {
|
|
compatible = "ti,omap5430-timer";
|
|
reg = <0x4ae18000 0x80>;
|
|
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
|
ti,hwmods = "timer1";
|
|
ti,timer-alwon;
|
|
};
|
|
|
|
timer2: timer@48032000 {
|
|
compatible = "ti,omap5430-timer";
|
|
reg = <0x48032000 0x80>;
|
|
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
|
|
ti,hwmods = "timer2";
|
|
};
|
|
|
|
timer3: timer@48034000 {
|
|
compatible = "ti,omap5430-timer";
|
|
reg = <0x48034000 0x80>;
|
|
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
|
|
ti,hwmods = "timer3";
|
|
};
|
|
|
|
timer4: timer@48036000 {
|
|
compatible = "ti,omap5430-timer";
|
|
reg = <0x48036000 0x80>;
|
|
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
|
|
ti,hwmods = "timer4";
|
|
};
|
|
|
|
timer5: timer@40138000 {
|
|
compatible = "ti,omap5430-timer";
|
|
reg = <0x40138000 0x80>,
|
|
<0x49038000 0x80>;
|
|
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
|
|
ti,hwmods = "timer5";
|
|
ti,timer-dsp;
|
|
ti,timer-pwm;
|
|
};
|
|
|
|
timer6: timer@4013a000 {
|
|
compatible = "ti,omap5430-timer";
|
|
reg = <0x4013a000 0x80>,
|
|
<0x4903a000 0x80>;
|
|
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
|
|
ti,hwmods = "timer6";
|
|
ti,timer-dsp;
|
|
ti,timer-pwm;
|
|
};
|
|
|
|
timer7: timer@4013c000 {
|
|
compatible = "ti,omap5430-timer";
|
|
reg = <0x4013c000 0x80>,
|
|
<0x4903c000 0x80>;
|
|
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
|
|
ti,hwmods = "timer7";
|
|
ti,timer-dsp;
|
|
};
|
|
|
|
timer8: timer@4013e000 {
|
|
compatible = "ti,omap5430-timer";
|
|
reg = <0x4013e000 0x80>,
|
|
<0x4903e000 0x80>;
|
|
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
|
|
ti,hwmods = "timer8";
|
|
ti,timer-dsp;
|
|
ti,timer-pwm;
|
|
};
|
|
|
|
timer9: timer@4803e000 {
|
|
compatible = "ti,omap5430-timer";
|
|
reg = <0x4803e000 0x80>;
|
|
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
|
|
ti,hwmods = "timer9";
|
|
ti,timer-pwm;
|
|
};
|
|
|
|
timer10: timer@48086000 {
|
|
compatible = "ti,omap5430-timer";
|
|
reg = <0x48086000 0x80>;
|
|
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
|
|
ti,hwmods = "timer10";
|
|
ti,timer-pwm;
|
|
};
|
|
|
|
timer11: timer@48088000 {
|
|
compatible = "ti,omap5430-timer";
|
|
reg = <0x48088000 0x80>;
|
|
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
|
|
ti,hwmods = "timer11";
|
|
ti,timer-pwm;
|
|
};
|
|
|
|
wdt2: wdt@4ae14000 {
|
|
compatible = "ti,omap5-wdt", "ti,omap3-wdt";
|
|
reg = <0x4ae14000 0x80>;
|
|
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
|
|
ti,hwmods = "wd_timer2";
|
|
};
|
|
|
|
dmm@4e000000 {
|
|
compatible = "ti,omap5-dmm";
|
|
reg = <0x4e000000 0x800>;
|
|
interrupts = <0 113 0x4>;
|
|
ti,hwmods = "dmm";
|
|
};
|
|
|
|
emif1: emif@4c000000 {
|
|
compatible = "ti,emif-4d5";
|
|
ti,hwmods = "emif1";
|
|
ti,no-idle-on-init;
|
|
phy-type = <2>; /* DDR PHY type: Intelli PHY */
|
|
reg = <0x4c000000 0x400>;
|
|
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
|
|
hw-caps-read-idle-ctrl;
|
|
hw-caps-ll-interface;
|
|
hw-caps-temp-alert;
|
|
};
|
|
|
|
emif2: emif@4d000000 {
|
|
compatible = "ti,emif-4d5";
|
|
ti,hwmods = "emif2";
|
|
ti,no-idle-on-init;
|
|
phy-type = <2>; /* DDR PHY type: Intelli PHY */
|
|
reg = <0x4d000000 0x400>;
|
|
interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
|
|
hw-caps-read-idle-ctrl;
|
|
hw-caps-ll-interface;
|
|
hw-caps-temp-alert;
|
|
};
|
|
|
|
omap_control_usb2phy: control-phy@4a002300 {
|
|
compatible = "ti,control-phy-usb2";
|
|
reg = <0x4a002300 0x4>;
|
|
reg-names = "power";
|
|
};
|
|
|
|
omap_control_usb3phy: control-phy@4a002370 {
|
|
compatible = "ti,control-phy-pipe3";
|
|
reg = <0x4a002370 0x4>;
|
|
reg-names = "power";
|
|
};
|
|
|
|
usb3: omap_dwc3@4a020000 {
|
|
compatible = "ti,dwc3";
|
|
ti,hwmods = "usb_otg_ss";
|
|
reg = <0x4a020000 0x10000>;
|
|
interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
utmi-mode = <2>;
|
|
ranges;
|
|
dwc3@4a030000 {
|
|
compatible = "snps,dwc3";
|
|
reg = <0x4a030000 0x10000>;
|
|
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
|
|
phys = <&usb2_phy>, <&usb3_phy>;
|
|
phy-names = "usb2-phy", "usb3-phy";
|
|
dr_mode = "peripheral";
|
|
tx-fifo-resize;
|
|
};
|
|
};
|
|
|
|
ocp2scp@4a080000 {
|
|
compatible = "ti,omap-ocp2scp";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
reg = <0x4a080000 0x20>;
|
|
ranges;
|
|
ti,hwmods = "ocp2scp1";
|
|
usb2_phy: usb2phy@4a084000 {
|
|
compatible = "ti,omap-usb2";
|
|
reg = <0x4a084000 0x7c>;
|
|
ctrl-module = <&omap_control_usb2phy>;
|
|
#phy-cells = <0>;
|
|
};
|
|
|
|
usb3_phy: usb3phy@4a084400 {
|
|
compatible = "ti,omap-usb3";
|
|
reg = <0x4a084400 0x80>,
|
|
<0x4a084800 0x64>,
|
|
<0x4a084c00 0x40>;
|
|
reg-names = "phy_rx", "phy_tx", "pll_ctrl";
|
|
ctrl-module = <&omap_control_usb3phy>;
|
|
clocks = <&usb_phy_cm_clk32k>,
|
|
<&sys_clkin>,
|
|
<&usb_otg_ss_refclk960m>;
|
|
clock-names = "wkupclk",
|
|
"sysclk",
|
|
"refclk";
|
|
#phy-cells = <0>;
|
|
};
|
|
};
|
|
|
|
usbhstll: usbhstll@4a062000 {
|
|
compatible = "ti,usbhs-tll";
|
|
reg = <0x4a062000 0x1000>;
|
|
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
|
|
ti,hwmods = "usb_tll_hs";
|
|
};
|
|
|
|
usbhshost: usbhshost@4a064000 {
|
|
compatible = "ti,usbhs-host";
|
|
reg = <0x4a064000 0x800>;
|
|
ti,hwmods = "usb_host_hs";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
clocks = <&l3init_60m_fclk>,
|
|
<&xclk60mhsp1_ck>,
|
|
<&xclk60mhsp2_ck>;
|
|
clock-names = "refclk_60m_int",
|
|
"refclk_60m_ext_p1",
|
|
"refclk_60m_ext_p2";
|
|
|
|
usbhsohci: ohci@4a064800 {
|
|
compatible = "ti,ohci-omap3";
|
|
reg = <0x4a064800 0x400>;
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
usbhsehci: ehci@4a064c00 {
|
|
compatible = "ti,ehci-omap";
|
|
reg = <0x4a064c00 0x400>;
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
};
|
|
|
|
bandgap: bandgap@4a0021e0 {
|
|
reg = <0x4a0021e0 0xc
|
|
0x4a00232c 0xc
|
|
0x4a002380 0x2c
|
|
0x4a0023C0 0x3c>;
|
|
interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
|
|
compatible = "ti,omap5430-bandgap";
|
|
|
|
#thermal-sensor-cells = <1>;
|
|
};
|
|
};
|
|
};
|
|
|
|
/include/ "omap54xx-clocks.dtsi"
|