forked from Minki/linux
f18cc2ff5e
OMAP interrupt controller goes to unknown state when there is right combination of l3,l4 sleep/wake-up transitions, l4 autoidle in interrupt controller and some interrupt. When this happens, interrupts are not delivered to ARM anymore and ARM will remain in WFI (wait for interrupt) until interrupt controller is forced to wake-up (i.e. lauterbach). Signed-off-by: Tero Kristo <tero.kristo@nokia.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
510 lines
17 KiB
C
510 lines
17 KiB
C
/*
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* arch/arm/plat-omap/include/mach/irqs.h
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*
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* Copyright (C) Greg Lonnon 2001
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* Updated for OMAP-1610 by Tony Lindgren <tony@atomide.com>
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*
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* Copyright (C) 2009 Texas Instruments
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* Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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* NOTE: The interrupt vectors for the OMAP-1509, OMAP-1510, and OMAP-1610
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* are different.
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*/
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#ifndef __ASM_ARCH_OMAP15XX_IRQS_H
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#define __ASM_ARCH_OMAP15XX_IRQS_H
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/*
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* IRQ numbers for interrupt handler 1
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*
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* NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below
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*
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*/
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#define INT_CAMERA 1
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#define INT_FIQ 3
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#define INT_RTDX 6
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#define INT_DSP_MMU_ABORT 7
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#define INT_HOST 8
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#define INT_ABORT 9
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#define INT_BRIDGE_PRIV 13
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#define INT_GPIO_BANK1 14
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#define INT_UART3 15
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#define INT_TIMER3 16
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#define INT_DMA_CH0_6 19
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#define INT_DMA_CH1_7 20
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#define INT_DMA_CH2_8 21
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#define INT_DMA_CH3 22
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#define INT_DMA_CH4 23
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#define INT_DMA_CH5 24
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#define INT_DMA_LCD 25
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#define INT_TIMER1 26
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#define INT_WD_TIMER 27
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#define INT_BRIDGE_PUB 28
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#define INT_TIMER2 30
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#define INT_LCD_CTRL 31
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/*
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* OMAP-1510 specific IRQ numbers for interrupt handler 1
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*/
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#define INT_1510_IH2_IRQ 0
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#define INT_1510_RES2 2
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#define INT_1510_SPI_TX 4
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#define INT_1510_SPI_RX 5
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#define INT_1510_DSP_MAILBOX1 10
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#define INT_1510_DSP_MAILBOX2 11
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#define INT_1510_RES12 12
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#define INT_1510_LB_MMU 17
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#define INT_1510_RES18 18
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#define INT_1510_LOCAL_BUS 29
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/*
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* OMAP-1610 specific IRQ numbers for interrupt handler 1
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*/
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#define INT_1610_IH2_IRQ 0
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#define INT_1610_IH2_FIQ 2
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#define INT_1610_McBSP2_TX 4
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#define INT_1610_McBSP2_RX 5
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#define INT_1610_DSP_MAILBOX1 10
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#define INT_1610_DSP_MAILBOX2 11
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#define INT_1610_LCD_LINE 12
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#define INT_1610_GPTIMER1 17
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#define INT_1610_GPTIMER2 18
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#define INT_1610_SSR_FIFO_0 29
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/*
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* OMAP-7xx specific IRQ numbers for interrupt handler 1
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*/
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#define INT_7XX_IH2_FIQ 0
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#define INT_7XX_IH2_IRQ 1
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#define INT_7XX_USB_NON_ISO 2
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#define INT_7XX_USB_ISO 3
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#define INT_7XX_ICR 4
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#define INT_7XX_EAC 5
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#define INT_7XX_GPIO_BANK1 6
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#define INT_7XX_GPIO_BANK2 7
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#define INT_7XX_GPIO_BANK3 8
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#define INT_7XX_McBSP2TX 10
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#define INT_7XX_McBSP2RX 11
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#define INT_7XX_McBSP2RX_OVF 12
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#define INT_7XX_LCD_LINE 14
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#define INT_7XX_GSM_PROTECT 15
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#define INT_7XX_TIMER3 16
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#define INT_7XX_GPIO_BANK5 17
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#define INT_7XX_GPIO_BANK6 18
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#define INT_7XX_SPGIO_WR 29
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/*
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* IRQ numbers for interrupt handler 2
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*
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* NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below
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*/
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#define IH2_BASE 32
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#define INT_KEYBOARD (1 + IH2_BASE)
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#define INT_uWireTX (2 + IH2_BASE)
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#define INT_uWireRX (3 + IH2_BASE)
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#define INT_I2C (4 + IH2_BASE)
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#define INT_MPUIO (5 + IH2_BASE)
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#define INT_USB_HHC_1 (6 + IH2_BASE)
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#define INT_McBSP3TX (10 + IH2_BASE)
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#define INT_McBSP3RX (11 + IH2_BASE)
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#define INT_McBSP1TX (12 + IH2_BASE)
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#define INT_McBSP1RX (13 + IH2_BASE)
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#define INT_UART1 (14 + IH2_BASE)
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#define INT_UART2 (15 + IH2_BASE)
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#define INT_BT_MCSI1TX (16 + IH2_BASE)
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#define INT_BT_MCSI1RX (17 + IH2_BASE)
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#define INT_SOSSI_MATCH (19 + IH2_BASE)
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#define INT_USB_W2FC (20 + IH2_BASE)
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#define INT_1WIRE (21 + IH2_BASE)
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#define INT_OS_TIMER (22 + IH2_BASE)
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#define INT_MMC (23 + IH2_BASE)
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#define INT_GAUGE_32K (24 + IH2_BASE)
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#define INT_RTC_TIMER (25 + IH2_BASE)
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#define INT_RTC_ALARM (26 + IH2_BASE)
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#define INT_MEM_STICK (27 + IH2_BASE)
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/*
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* OMAP-1510 specific IRQ numbers for interrupt handler 2
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*/
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#define INT_1510_DSP_MMU (28 + IH2_BASE)
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#define INT_1510_COM_SPI_RO (31 + IH2_BASE)
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/*
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* OMAP-1610 specific IRQ numbers for interrupt handler 2
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*/
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#define INT_1610_FAC (0 + IH2_BASE)
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#define INT_1610_USB_HHC_2 (7 + IH2_BASE)
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#define INT_1610_USB_OTG (8 + IH2_BASE)
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#define INT_1610_SoSSI (9 + IH2_BASE)
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#define INT_1610_SoSSI_MATCH (19 + IH2_BASE)
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#define INT_1610_DSP_MMU (28 + IH2_BASE)
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#define INT_1610_McBSP2RX_OF (31 + IH2_BASE)
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#define INT_1610_STI (32 + IH2_BASE)
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#define INT_1610_STI_WAKEUP (33 + IH2_BASE)
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#define INT_1610_GPTIMER3 (34 + IH2_BASE)
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#define INT_1610_GPTIMER4 (35 + IH2_BASE)
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#define INT_1610_GPTIMER5 (36 + IH2_BASE)
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#define INT_1610_GPTIMER6 (37 + IH2_BASE)
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#define INT_1610_GPTIMER7 (38 + IH2_BASE)
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#define INT_1610_GPTIMER8 (39 + IH2_BASE)
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#define INT_1610_GPIO_BANK2 (40 + IH2_BASE)
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#define INT_1610_GPIO_BANK3 (41 + IH2_BASE)
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#define INT_1610_MMC2 (42 + IH2_BASE)
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#define INT_1610_CF (43 + IH2_BASE)
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#define INT_1610_WAKE_UP_REQ (46 + IH2_BASE)
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#define INT_1610_GPIO_BANK4 (48 + IH2_BASE)
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#define INT_1610_SPI (49 + IH2_BASE)
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#define INT_1610_DMA_CH6 (53 + IH2_BASE)
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#define INT_1610_DMA_CH7 (54 + IH2_BASE)
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#define INT_1610_DMA_CH8 (55 + IH2_BASE)
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#define INT_1610_DMA_CH9 (56 + IH2_BASE)
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#define INT_1610_DMA_CH10 (57 + IH2_BASE)
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#define INT_1610_DMA_CH11 (58 + IH2_BASE)
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#define INT_1610_DMA_CH12 (59 + IH2_BASE)
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#define INT_1610_DMA_CH13 (60 + IH2_BASE)
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#define INT_1610_DMA_CH14 (61 + IH2_BASE)
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#define INT_1610_DMA_CH15 (62 + IH2_BASE)
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#define INT_1610_NAND (63 + IH2_BASE)
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#define INT_1610_SHA1MD5 (91 + IH2_BASE)
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/*
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* OMAP-7xx specific IRQ numbers for interrupt handler 2
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*/
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#define INT_7XX_HW_ERRORS (0 + IH2_BASE)
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#define INT_7XX_NFIQ_PWR_FAIL (1 + IH2_BASE)
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#define INT_7XX_CFCD (2 + IH2_BASE)
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#define INT_7XX_CFIREQ (3 + IH2_BASE)
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#define INT_7XX_I2C (4 + IH2_BASE)
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#define INT_7XX_PCC (5 + IH2_BASE)
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#define INT_7XX_MPU_EXT_NIRQ (6 + IH2_BASE)
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#define INT_7XX_SPI_100K_1 (7 + IH2_BASE)
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#define INT_7XX_SYREN_SPI (8 + IH2_BASE)
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#define INT_7XX_VLYNQ (9 + IH2_BASE)
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#define INT_7XX_GPIO_BANK4 (10 + IH2_BASE)
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#define INT_7XX_McBSP1TX (11 + IH2_BASE)
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#define INT_7XX_McBSP1RX (12 + IH2_BASE)
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#define INT_7XX_McBSP1RX_OF (13 + IH2_BASE)
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#define INT_7XX_UART_MODEM_IRDA_2 (14 + IH2_BASE)
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#define INT_7XX_UART_MODEM_1 (15 + IH2_BASE)
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#define INT_7XX_MCSI (16 + IH2_BASE)
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#define INT_7XX_uWireTX (17 + IH2_BASE)
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#define INT_7XX_uWireRX (18 + IH2_BASE)
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#define INT_7XX_SMC_CD (19 + IH2_BASE)
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#define INT_7XX_SMC_IREQ (20 + IH2_BASE)
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#define INT_7XX_HDQ_1WIRE (21 + IH2_BASE)
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#define INT_7XX_TIMER32K (22 + IH2_BASE)
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#define INT_7XX_MMC_SDIO (23 + IH2_BASE)
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#define INT_7XX_UPLD (24 + IH2_BASE)
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#define INT_7XX_USB_HHC_1 (27 + IH2_BASE)
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#define INT_7XX_USB_HHC_2 (28 + IH2_BASE)
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#define INT_7XX_USB_GENI (29 + IH2_BASE)
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#define INT_7XX_USB_OTG (30 + IH2_BASE)
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#define INT_7XX_CAMERA_IF (31 + IH2_BASE)
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#define INT_7XX_RNG (32 + IH2_BASE)
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#define INT_7XX_DUAL_MODE_TIMER (33 + IH2_BASE)
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#define INT_7XX_DBB_RF_EN (34 + IH2_BASE)
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#define INT_7XX_MPUIO_KEYPAD (35 + IH2_BASE)
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#define INT_7XX_SHA1_MD5 (36 + IH2_BASE)
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#define INT_7XX_SPI_100K_2 (37 + IH2_BASE)
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#define INT_7XX_RNG_IDLE (38 + IH2_BASE)
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#define INT_7XX_MPUIO (39 + IH2_BASE)
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#define INT_7XX_LLPC_LCD_CTRL_CAN_BE_OFF (40 + IH2_BASE)
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#define INT_7XX_LLPC_OE_FALLING (41 + IH2_BASE)
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#define INT_7XX_LLPC_OE_RISING (42 + IH2_BASE)
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#define INT_7XX_LLPC_VSYNC (43 + IH2_BASE)
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#define INT_7XX_WAKE_UP_REQ (46 + IH2_BASE)
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#define INT_7XX_DMA_CH6 (53 + IH2_BASE)
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#define INT_7XX_DMA_CH7 (54 + IH2_BASE)
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#define INT_7XX_DMA_CH8 (55 + IH2_BASE)
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#define INT_7XX_DMA_CH9 (56 + IH2_BASE)
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#define INT_7XX_DMA_CH10 (57 + IH2_BASE)
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#define INT_7XX_DMA_CH11 (58 + IH2_BASE)
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#define INT_7XX_DMA_CH12 (59 + IH2_BASE)
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#define INT_7XX_DMA_CH13 (60 + IH2_BASE)
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#define INT_7XX_DMA_CH14 (61 + IH2_BASE)
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#define INT_7XX_DMA_CH15 (62 + IH2_BASE)
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#define INT_7XX_NAND (63 + IH2_BASE)
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#define INT_24XX_SYS_NIRQ 7
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#define INT_24XX_SDMA_IRQ0 12
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#define INT_24XX_SDMA_IRQ1 13
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#define INT_24XX_SDMA_IRQ2 14
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#define INT_24XX_SDMA_IRQ3 15
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#define INT_24XX_CAM_IRQ 24
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#define INT_24XX_DSS_IRQ 25
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#define INT_24XX_MAIL_U0_MPU 26
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#define INT_24XX_DSP_UMA 27
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#define INT_24XX_DSP_MMU 28
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#define INT_24XX_GPIO_BANK1 29
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#define INT_24XX_GPIO_BANK2 30
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#define INT_24XX_GPIO_BANK3 31
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#define INT_24XX_GPIO_BANK4 32
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#define INT_24XX_GPIO_BANK5 33
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#define INT_24XX_MAIL_U3_MPU 34
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#define INT_24XX_GPTIMER1 37
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#define INT_24XX_GPTIMER2 38
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#define INT_24XX_GPTIMER3 39
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#define INT_24XX_GPTIMER4 40
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#define INT_24XX_GPTIMER5 41
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#define INT_24XX_GPTIMER6 42
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#define INT_24XX_GPTIMER7 43
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#define INT_24XX_GPTIMER8 44
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#define INT_24XX_GPTIMER9 45
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#define INT_24XX_GPTIMER10 46
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#define INT_24XX_GPTIMER11 47
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#define INT_24XX_GPTIMER12 48
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#define INT_24XX_SHA1MD5 51
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#define INT_24XX_MCBSP4_IRQ_TX 54
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#define INT_24XX_MCBSP4_IRQ_RX 55
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#define INT_24XX_I2C1_IRQ 56
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#define INT_24XX_I2C2_IRQ 57
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#define INT_24XX_HDQ_IRQ 58
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#define INT_24XX_MCBSP1_IRQ_TX 59
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#define INT_24XX_MCBSP1_IRQ_RX 60
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#define INT_24XX_MCBSP2_IRQ_TX 62
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#define INT_24XX_MCBSP2_IRQ_RX 63
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#define INT_24XX_SPI1_IRQ 65
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#define INT_24XX_SPI2_IRQ 66
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#define INT_24XX_UART1_IRQ 72
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#define INT_24XX_UART2_IRQ 73
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#define INT_24XX_UART3_IRQ 74
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#define INT_24XX_USB_IRQ_GEN 75
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#define INT_24XX_USB_IRQ_NISO 76
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#define INT_24XX_USB_IRQ_ISO 77
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#define INT_24XX_USB_IRQ_HGEN 78
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#define INT_24XX_USB_IRQ_HSOF 79
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#define INT_24XX_USB_IRQ_OTG 80
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#define INT_24XX_MCBSP5_IRQ_TX 81
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#define INT_24XX_MCBSP5_IRQ_RX 82
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#define INT_24XX_MMC_IRQ 83
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#define INT_24XX_MMC2_IRQ 86
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#define INT_24XX_MCBSP3_IRQ_TX 89
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#define INT_24XX_MCBSP3_IRQ_RX 90
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#define INT_24XX_SPI3_IRQ 91
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#define INT_243X_MCBSP2_IRQ 16
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#define INT_243X_MCBSP3_IRQ 17
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#define INT_243X_MCBSP4_IRQ 18
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#define INT_243X_MCBSP5_IRQ 19
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#define INT_243X_MCBSP1_IRQ 64
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#define INT_243X_HS_USB_MC 92
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#define INT_243X_HS_USB_DMA 93
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#define INT_243X_CARKIT_IRQ 94
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#define INT_34XX_BENCH_MPU_EMUL 3
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#define INT_34XX_ST_MCBSP2_IRQ 4
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#define INT_34XX_ST_MCBSP3_IRQ 5
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#define INT_34XX_SSM_ABORT_IRQ 6
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#define INT_34XX_SYS_NIRQ 7
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#define INT_34XX_D2D_FW_IRQ 8
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#define INT_34XX_PRCM_MPU_IRQ 11
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#define INT_34XX_MCBSP1_IRQ 16
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#define INT_34XX_MCBSP2_IRQ 17
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#define INT_34XX_MCBSP3_IRQ 22
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#define INT_34XX_MCBSP4_IRQ 23
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#define INT_34XX_CAM_IRQ 24
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#define INT_34XX_MCBSP5_IRQ 27
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#define INT_34XX_GPIO_BANK1 29
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#define INT_34XX_GPIO_BANK2 30
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#define INT_34XX_GPIO_BANK3 31
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#define INT_34XX_GPIO_BANK4 32
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#define INT_34XX_GPIO_BANK5 33
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#define INT_34XX_GPIO_BANK6 34
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#define INT_34XX_USIM_IRQ 35
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#define INT_34XX_WDT3_IRQ 36
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#define INT_34XX_SPI4_IRQ 48
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#define INT_34XX_SHA1MD52_IRQ 49
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#define INT_34XX_FPKA_READY_IRQ 50
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#define INT_34XX_SHA1MD51_IRQ 51
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#define INT_34XX_RNG_IRQ 52
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#define INT_34XX_I2C3_IRQ 61
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#define INT_34XX_FPKA_ERROR_IRQ 64
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#define INT_34XX_PBIAS_IRQ 75
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#define INT_34XX_OHCI_IRQ 76
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#define INT_34XX_EHCI_IRQ 77
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#define INT_34XX_TLL_IRQ 78
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#define INT_34XX_PARTHASH_IRQ 79
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#define INT_34XX_MMC3_IRQ 94
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#define INT_34XX_GPT12_IRQ 95
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#define INT_34XX_BENCH_MPU_EMUL 3
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#define IRQ_GIC_START 32
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#define INT_44XX_LOCALTIMER_IRQ 29
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#define INT_44XX_LOCALWDT_IRQ 30
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#define INT_44XX_BENCH_MPU_EMUL (3 + IRQ_GIC_START)
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#define INT_44XX_SSM_ABORT_IRQ (6 + IRQ_GIC_START)
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#define INT_44XX_SYS_NIRQ (7 + IRQ_GIC_START)
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#define INT_44XX_D2D_FW_IRQ (8 + IRQ_GIC_START)
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#define INT_44XX_PRCM_MPU_IRQ (11 + IRQ_GIC_START)
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#define INT_44XX_SDMA_IRQ0 (12 + IRQ_GIC_START)
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#define INT_44XX_SDMA_IRQ1 (13 + IRQ_GIC_START)
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#define INT_44XX_SDMA_IRQ2 (14 + IRQ_GIC_START)
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#define INT_44XX_SDMA_IRQ3 (15 + IRQ_GIC_START)
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#define INT_44XX_ISS_IRQ (24 + IRQ_GIC_START)
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#define INT_44XX_DSS_IRQ (25 + IRQ_GIC_START)
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#define INT_44XX_MAIL_U0_MPU (26 + IRQ_GIC_START)
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#define INT_44XX_DSP_MMU (28 + IRQ_GIC_START)
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#define INT_44XX_GPTIMER1 (37 + IRQ_GIC_START)
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#define INT_44XX_GPTIMER2 (38 + IRQ_GIC_START)
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#define INT_44XX_GPTIMER3 (39 + IRQ_GIC_START)
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#define INT_44XX_GPTIMER4 (40 + IRQ_GIC_START)
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#define INT_44XX_GPTIMER5 (41 + IRQ_GIC_START)
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#define INT_44XX_GPTIMER6 (42 + IRQ_GIC_START)
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#define INT_44XX_GPTIMER7 (43 + IRQ_GIC_START)
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#define INT_44XX_GPTIMER8 (44 + IRQ_GIC_START)
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#define INT_44XX_GPTIMER9 (45 + IRQ_GIC_START)
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#define INT_44XX_GPTIMER10 (46 + IRQ_GIC_START)
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#define INT_44XX_GPTIMER11 (47 + IRQ_GIC_START)
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#define INT_44XX_GPTIMER12 (95 + IRQ_GIC_START)
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#define INT_44XX_SHA1MD5 (51 + IRQ_GIC_START)
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#define INT_44XX_I2C1_IRQ (56 + IRQ_GIC_START)
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#define INT_44XX_I2C2_IRQ (57 + IRQ_GIC_START)
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#define INT_44XX_HDQ_IRQ (58 + IRQ_GIC_START)
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#define INT_44XX_SPI1_IRQ (65 + IRQ_GIC_START)
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#define INT_44XX_SPI2_IRQ (66 + IRQ_GIC_START)
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#define INT_44XX_HSI_1_IRQ0 (67 + IRQ_GIC_START)
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#define INT_44XX_HSI_2_IRQ1 (68 + IRQ_GIC_START)
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#define INT_44XX_HSI_1_DMAIRQ (71 + IRQ_GIC_START)
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#define INT_44XX_UART1_IRQ (72 + IRQ_GIC_START)
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#define INT_44XX_UART2_IRQ (73 + IRQ_GIC_START)
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#define INT_44XX_UART3_IRQ (74 + IRQ_GIC_START)
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#define INT_44XX_UART4_IRQ (70 + IRQ_GIC_START)
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#define INT_44XX_USB_IRQ_NISO (76 + IRQ_GIC_START)
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#define INT_44XX_USB_IRQ_ISO (77 + IRQ_GIC_START)
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#define INT_44XX_USB_IRQ_HGEN (78 + IRQ_GIC_START)
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#define INT_44XX_USB_IRQ_HSOF (79 + IRQ_GIC_START)
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#define INT_44XX_USB_IRQ_OTG (80 + IRQ_GIC_START)
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#define INT_44XX_MCBSP4_IRQ_TX (81 + IRQ_GIC_START)
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#define INT_44XX_MCBSP4_IRQ_RX (82 + IRQ_GIC_START)
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#define INT_44XX_MMC_IRQ (83 + IRQ_GIC_START)
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#define INT_44XX_MMC2_IRQ (86 + IRQ_GIC_START)
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#define INT_44XX_MCBSP2_IRQ_TX (89 + IRQ_GIC_START)
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#define INT_44XX_MCBSP2_IRQ_RX (90 + IRQ_GIC_START)
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#define INT_44XX_SPI3_IRQ (91 + IRQ_GIC_START)
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#define INT_44XX_SPI5_IRQ (69 + IRQ_GIC_START)
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#define INT_44XX_MCBSP5_IRQ (16 + IRQ_GIC_START)
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#define INT_44xX_MCBSP1_IRQ (17 + IRQ_GIC_START)
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#define INT_44XX_MCBSP2_IRQ (22 + IRQ_GIC_START)
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#define INT_44XX_MCBSP3_IRQ (23 + IRQ_GIC_START)
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#define INT_44XX_MCBSP4_IRQ (27 + IRQ_GIC_START)
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#define INT_44XX_HS_USB_MC (92 + IRQ_GIC_START)
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#define INT_44XX_HS_USB_DMA (93 + IRQ_GIC_START)
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#define INT_44XX_GPIO_BANK1 (29 + IRQ_GIC_START)
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#define INT_44XX_GPIO_BANK2 (30 + IRQ_GIC_START)
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#define INT_44XX_GPIO_BANK3 (31 + IRQ_GIC_START)
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#define INT_44XX_GPIO_BANK4 (32 + IRQ_GIC_START)
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#define INT_44XX_GPIO_BANK5 (33 + IRQ_GIC_START)
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#define INT_44XX_GPIO_BANK6 (34 + IRQ_GIC_START)
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#define INT_44XX_USIM_IRQ (35 + IRQ_GIC_START)
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#define INT_44XX_WDT3_IRQ (36 + IRQ_GIC_START)
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#define INT_44XX_SPI4_IRQ (48 + IRQ_GIC_START)
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#define INT_44XX_SHA1MD52_IRQ (49 + IRQ_GIC_START)
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#define INT_44XX_FPKA_READY_IRQ (50 + IRQ_GIC_START)
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#define INT_44XX_SHA1MD51_IRQ (51 + IRQ_GIC_START)
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#define INT_44XX_RNG_IRQ (52 + IRQ_GIC_START)
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#define INT_44XX_MMC5_IRQ (59 + IRQ_GIC_START)
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#define INT_44XX_I2C3_IRQ (61 + IRQ_GIC_START)
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#define INT_44XX_FPKA_ERROR_IRQ (64 + IRQ_GIC_START)
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#define INT_44XX_PBIAS_IRQ (75 + IRQ_GIC_START)
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#define INT_44XX_OHCI_IRQ (76 + IRQ_GIC_START)
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#define INT_44XX_EHCI_IRQ (77 + IRQ_GIC_START)
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#define INT_44XX_TLL_IRQ (78 + IRQ_GIC_START)
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#define INT_44XX_PARTHASH_IRQ (79 + IRQ_GIC_START)
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#define INT_44XX_MMC3_IRQ (94 + IRQ_GIC_START)
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#define INT_44XX_MMC4_IRQ (96 + IRQ_GIC_START)
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/* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730/850) and
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* 16 MPUIO lines */
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#define OMAP_MAX_GPIO_LINES 192
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#define IH_GPIO_BASE (128 + IH2_BASE)
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#define IH_MPUIO_BASE (OMAP_MAX_GPIO_LINES + IH_GPIO_BASE)
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#define OMAP_IRQ_END (IH_MPUIO_BASE + 16)
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/* External FPGA handles interrupts on Innovator boards */
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#define OMAP_FPGA_IRQ_BASE (OMAP_IRQ_END)
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#ifdef CONFIG_MACH_OMAP_INNOVATOR
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#define OMAP_FPGA_NR_IRQS 24
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#else
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#define OMAP_FPGA_NR_IRQS 0
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#endif
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#define OMAP_FPGA_IRQ_END (OMAP_FPGA_IRQ_BASE + OMAP_FPGA_NR_IRQS)
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/* External TWL4030 can handle interrupts on 2430 and 34xx boards */
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#define TWL4030_IRQ_BASE (OMAP_FPGA_IRQ_END)
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#ifdef CONFIG_TWL4030_CORE
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#define TWL4030_BASE_NR_IRQS 8
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#define TWL4030_PWR_NR_IRQS 8
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#else
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#define TWL4030_BASE_NR_IRQS 0
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#define TWL4030_PWR_NR_IRQS 0
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#endif
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#define TWL4030_IRQ_END (TWL4030_IRQ_BASE + TWL4030_BASE_NR_IRQS)
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#define TWL4030_PWR_IRQ_BASE TWL4030_IRQ_END
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#define TWL4030_PWR_IRQ_END (TWL4030_PWR_IRQ_BASE + TWL4030_PWR_NR_IRQS)
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/* External TWL4030 gpio interrupts are optional */
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#define TWL4030_GPIO_IRQ_BASE TWL4030_PWR_IRQ_END
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#ifdef CONFIG_GPIO_TWL4030
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#define TWL4030_GPIO_NR_IRQS 18
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#else
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#define TWL4030_GPIO_NR_IRQS 0
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#endif
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#define TWL4030_GPIO_IRQ_END (TWL4030_GPIO_IRQ_BASE + TWL4030_GPIO_NR_IRQS)
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#define TWL6030_IRQ_BASE (OMAP_FPGA_IRQ_END)
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#ifdef CONFIG_TWL4030_CORE
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#define TWL6030_BASE_NR_IRQS 20
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#else
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#define TWL6030_BASE_NR_IRQS 0
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#endif
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#define TWL6030_IRQ_END (TWL6030_IRQ_BASE + TWL6030_BASE_NR_IRQS)
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/* Total number of interrupts depends on the enabled blocks above */
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#if (TWL4030_GPIO_IRQ_END > TWL6030_IRQ_END)
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#define TWL_IRQ_END TWL4030_GPIO_IRQ_END
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#else
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#define TWL_IRQ_END TWL6030_IRQ_END
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#endif
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#define NR_IRQS TWL_IRQ_END
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|
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#define OMAP_IRQ_BIT(irq) (1 << ((irq) % 32))
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|
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#define INTCPS_NR_MIR_REGS 3
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#define INTCPS_NR_IRQS 96
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#ifndef __ASSEMBLY__
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extern void omap_init_irq(void);
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extern int omap_irq_pending(void);
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void omap_intc_save_context(void);
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|
void omap_intc_restore_context(void);
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|
void omap3_intc_suspend(void);
|
|
void omap3_intc_prepare_idle(void);
|
|
void omap3_intc_resume_idle(void);
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|
#endif
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#include <mach/hardware.h>
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#endif
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