forked from Minki/linux
9c95f11b9e
The current code initializes the timing registers at very time we call the gpmi_begin(). This really wastes the cpu cycles. Add a new flag to let the gpmi driver initializes the timing registers only one time. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
1330 lines
40 KiB
C
1330 lines
40 KiB
C
/*
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* Freescale GPMI NAND Flash Driver
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*
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* Copyright (C) 2008-2011 Freescale Semiconductor, Inc.
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* Copyright (C) 2008 Embedded Alley Solutions, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*/
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#include <linux/mtd/gpmi-nand.h>
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#include <linux/delay.h>
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#include <linux/clk.h>
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#include "gpmi-nand.h"
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#include "gpmi-regs.h"
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#include "bch-regs.h"
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static struct timing_threshod timing_default_threshold = {
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.max_data_setup_cycles = (BM_GPMI_TIMING0_DATA_SETUP >>
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BP_GPMI_TIMING0_DATA_SETUP),
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.internal_data_setup_in_ns = 0,
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.max_sample_delay_factor = (BM_GPMI_CTRL1_RDN_DELAY >>
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BP_GPMI_CTRL1_RDN_DELAY),
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.max_dll_clock_period_in_ns = 32,
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.max_dll_delay_in_ns = 16,
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};
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#define MXS_SET_ADDR 0x4
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#define MXS_CLR_ADDR 0x8
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/*
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* Clear the bit and poll it cleared. This is usually called with
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* a reset address and mask being either SFTRST(bit 31) or CLKGATE
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* (bit 30).
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*/
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static int clear_poll_bit(void __iomem *addr, u32 mask)
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{
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int timeout = 0x400;
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/* clear the bit */
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writel(mask, addr + MXS_CLR_ADDR);
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/*
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* SFTRST needs 3 GPMI clocks to settle, the reference manual
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* recommends to wait 1us.
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*/
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udelay(1);
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/* poll the bit becoming clear */
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while ((readl(addr) & mask) && --timeout)
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/* nothing */;
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return !timeout;
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}
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#define MODULE_CLKGATE (1 << 30)
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#define MODULE_SFTRST (1 << 31)
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/*
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* The current mxs_reset_block() will do two things:
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* [1] enable the module.
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* [2] reset the module.
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*
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* In most of the cases, it's ok.
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* But in MX23, there is a hardware bug in the BCH block (see erratum #2847).
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* If you try to soft reset the BCH block, it becomes unusable until
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* the next hard reset. This case occurs in the NAND boot mode. When the board
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* boots by NAND, the ROM of the chip will initialize the BCH blocks itself.
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* So If the driver tries to reset the BCH again, the BCH will not work anymore.
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* You will see a DMA timeout in this case. The bug has been fixed
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* in the following chips, such as MX28.
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*
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* To avoid this bug, just add a new parameter `just_enable` for
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* the mxs_reset_block(), and rewrite it here.
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*/
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static int gpmi_reset_block(void __iomem *reset_addr, bool just_enable)
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{
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int ret;
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int timeout = 0x400;
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/* clear and poll SFTRST */
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ret = clear_poll_bit(reset_addr, MODULE_SFTRST);
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if (unlikely(ret))
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goto error;
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/* clear CLKGATE */
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writel(MODULE_CLKGATE, reset_addr + MXS_CLR_ADDR);
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if (!just_enable) {
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/* set SFTRST to reset the block */
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writel(MODULE_SFTRST, reset_addr + MXS_SET_ADDR);
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udelay(1);
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/* poll CLKGATE becoming set */
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while ((!(readl(reset_addr) & MODULE_CLKGATE)) && --timeout)
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/* nothing */;
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if (unlikely(!timeout))
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goto error;
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}
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/* clear and poll SFTRST */
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ret = clear_poll_bit(reset_addr, MODULE_SFTRST);
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if (unlikely(ret))
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goto error;
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/* clear and poll CLKGATE */
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ret = clear_poll_bit(reset_addr, MODULE_CLKGATE);
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if (unlikely(ret))
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goto error;
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return 0;
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error:
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pr_err("%s(%p): module reset timeout\n", __func__, reset_addr);
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return -ETIMEDOUT;
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}
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static int __gpmi_enable_clk(struct gpmi_nand_data *this, bool v)
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{
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struct clk *clk;
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int ret;
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int i;
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for (i = 0; i < GPMI_CLK_MAX; i++) {
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clk = this->resources.clock[i];
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if (!clk)
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break;
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if (v) {
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ret = clk_prepare_enable(clk);
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if (ret)
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goto err_clk;
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} else {
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clk_disable_unprepare(clk);
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}
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}
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return 0;
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err_clk:
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for (; i > 0; i--)
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clk_disable_unprepare(this->resources.clock[i - 1]);
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return ret;
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}
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#define gpmi_enable_clk(x) __gpmi_enable_clk(x, true)
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#define gpmi_disable_clk(x) __gpmi_enable_clk(x, false)
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int gpmi_init(struct gpmi_nand_data *this)
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{
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struct resources *r = &this->resources;
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int ret;
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ret = gpmi_enable_clk(this);
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if (ret)
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goto err_out;
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ret = gpmi_reset_block(r->gpmi_regs, false);
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if (ret)
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goto err_out;
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/* Choose NAND mode. */
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writel(BM_GPMI_CTRL1_GPMI_MODE, r->gpmi_regs + HW_GPMI_CTRL1_CLR);
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/* Set the IRQ polarity. */
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writel(BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY,
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r->gpmi_regs + HW_GPMI_CTRL1_SET);
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/* Disable Write-Protection. */
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writel(BM_GPMI_CTRL1_DEV_RESET, r->gpmi_regs + HW_GPMI_CTRL1_SET);
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/* Select BCH ECC. */
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writel(BM_GPMI_CTRL1_BCH_MODE, r->gpmi_regs + HW_GPMI_CTRL1_SET);
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gpmi_disable_clk(this);
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return 0;
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err_out:
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return ret;
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}
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/* This function is very useful. It is called only when the bug occur. */
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void gpmi_dump_info(struct gpmi_nand_data *this)
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{
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struct resources *r = &this->resources;
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struct bch_geometry *geo = &this->bch_geometry;
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u32 reg;
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int i;
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pr_err("Show GPMI registers :\n");
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for (i = 0; i <= HW_GPMI_DEBUG / 0x10 + 1; i++) {
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reg = readl(r->gpmi_regs + i * 0x10);
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pr_err("offset 0x%.3x : 0x%.8x\n", i * 0x10, reg);
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}
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/* start to print out the BCH info */
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pr_err("BCH Geometry :\n");
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pr_err("GF length : %u\n", geo->gf_len);
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pr_err("ECC Strength : %u\n", geo->ecc_strength);
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pr_err("Page Size in Bytes : %u\n", geo->page_size);
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pr_err("Metadata Size in Bytes : %u\n", geo->metadata_size);
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pr_err("ECC Chunk Size in Bytes: %u\n", geo->ecc_chunk_size);
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pr_err("ECC Chunk Count : %u\n", geo->ecc_chunk_count);
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pr_err("Payload Size in Bytes : %u\n", geo->payload_size);
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pr_err("Auxiliary Size in Bytes: %u\n", geo->auxiliary_size);
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pr_err("Auxiliary Status Offset: %u\n", geo->auxiliary_status_offset);
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pr_err("Block Mark Byte Offset : %u\n", geo->block_mark_byte_offset);
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pr_err("Block Mark Bit Offset : %u\n", geo->block_mark_bit_offset);
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}
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/* Configures the geometry for BCH. */
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int bch_set_geometry(struct gpmi_nand_data *this)
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{
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struct resources *r = &this->resources;
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struct bch_geometry *bch_geo = &this->bch_geometry;
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unsigned int block_count;
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unsigned int block_size;
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unsigned int metadata_size;
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unsigned int ecc_strength;
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unsigned int page_size;
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int ret;
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if (common_nfc_set_geometry(this))
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return !0;
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block_count = bch_geo->ecc_chunk_count - 1;
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block_size = bch_geo->ecc_chunk_size;
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metadata_size = bch_geo->metadata_size;
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ecc_strength = bch_geo->ecc_strength >> 1;
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page_size = bch_geo->page_size;
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ret = gpmi_enable_clk(this);
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if (ret)
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goto err_out;
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/*
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* Due to erratum #2847 of the MX23, the BCH cannot be soft reset on this
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* chip, otherwise it will lock up. So we skip resetting BCH on the MX23.
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* On the other hand, the MX28 needs the reset, because one case has been
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* seen where the BCH produced ECC errors constantly after 10000
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* consecutive reboots. The latter case has not been seen on the MX23 yet,
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* still we don't know if it could happen there as well.
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*/
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ret = gpmi_reset_block(r->bch_regs, GPMI_IS_MX23(this));
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if (ret)
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goto err_out;
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/* Configure layout 0. */
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writel(BF_BCH_FLASH0LAYOUT0_NBLOCKS(block_count)
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| BF_BCH_FLASH0LAYOUT0_META_SIZE(metadata_size)
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| BF_BCH_FLASH0LAYOUT0_ECC0(ecc_strength, this)
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| BF_BCH_FLASH0LAYOUT0_DATA0_SIZE(block_size, this),
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r->bch_regs + HW_BCH_FLASH0LAYOUT0);
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writel(BF_BCH_FLASH0LAYOUT1_PAGE_SIZE(page_size)
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| BF_BCH_FLASH0LAYOUT1_ECCN(ecc_strength, this)
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| BF_BCH_FLASH0LAYOUT1_DATAN_SIZE(block_size, this),
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r->bch_regs + HW_BCH_FLASH0LAYOUT1);
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/* Set *all* chip selects to use layout 0. */
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writel(0, r->bch_regs + HW_BCH_LAYOUTSELECT);
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/* Enable interrupts. */
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writel(BM_BCH_CTRL_COMPLETE_IRQ_EN,
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r->bch_regs + HW_BCH_CTRL_SET);
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gpmi_disable_clk(this);
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return 0;
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err_out:
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return ret;
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}
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/* Converts time in nanoseconds to cycles. */
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static unsigned int ns_to_cycles(unsigned int time,
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unsigned int period, unsigned int min)
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{
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unsigned int k;
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k = (time + period - 1) / period;
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return max(k, min);
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}
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#define DEF_MIN_PROP_DELAY 5
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#define DEF_MAX_PROP_DELAY 9
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/* Apply timing to current hardware conditions. */
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static int gpmi_nfc_compute_hardware_timing(struct gpmi_nand_data *this,
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struct gpmi_nfc_hardware_timing *hw)
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{
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struct timing_threshod *nfc = &timing_default_threshold;
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struct resources *r = &this->resources;
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struct nand_chip *nand = &this->nand;
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struct nand_timing target = this->timing;
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bool improved_timing_is_available;
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unsigned long clock_frequency_in_hz;
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unsigned int clock_period_in_ns;
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bool dll_use_half_periods;
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unsigned int dll_delay_shift;
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unsigned int max_sample_delay_in_ns;
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unsigned int address_setup_in_cycles;
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unsigned int data_setup_in_ns;
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unsigned int data_setup_in_cycles;
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unsigned int data_hold_in_cycles;
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int ideal_sample_delay_in_ns;
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unsigned int sample_delay_factor;
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int tEYE;
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unsigned int min_prop_delay_in_ns = DEF_MIN_PROP_DELAY;
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unsigned int max_prop_delay_in_ns = DEF_MAX_PROP_DELAY;
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/*
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* If there are multiple chips, we need to relax the timings to allow
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* for signal distortion due to higher capacitance.
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*/
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if (nand->numchips > 2) {
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target.data_setup_in_ns += 10;
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target.data_hold_in_ns += 10;
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target.address_setup_in_ns += 10;
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} else if (nand->numchips > 1) {
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target.data_setup_in_ns += 5;
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target.data_hold_in_ns += 5;
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target.address_setup_in_ns += 5;
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}
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/* Check if improved timing information is available. */
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improved_timing_is_available =
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(target.tREA_in_ns >= 0) &&
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(target.tRLOH_in_ns >= 0) &&
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(target.tRHOH_in_ns >= 0) ;
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/* Inspect the clock. */
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nfc->clock_frequency_in_hz = clk_get_rate(r->clock[0]);
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clock_frequency_in_hz = nfc->clock_frequency_in_hz;
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clock_period_in_ns = NSEC_PER_SEC / clock_frequency_in_hz;
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/*
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* The NFC quantizes setup and hold parameters in terms of clock cycles.
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* Here, we quantize the setup and hold timing parameters to the
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* next-highest clock period to make sure we apply at least the
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* specified times.
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*
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* For data setup and data hold, the hardware interprets a value of zero
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* as the largest possible delay. This is not what's intended by a zero
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* in the input parameter, so we impose a minimum of one cycle.
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*/
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data_setup_in_cycles = ns_to_cycles(target.data_setup_in_ns,
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clock_period_in_ns, 1);
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data_hold_in_cycles = ns_to_cycles(target.data_hold_in_ns,
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clock_period_in_ns, 1);
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address_setup_in_cycles = ns_to_cycles(target.address_setup_in_ns,
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clock_period_in_ns, 0);
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/*
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* The clock's period affects the sample delay in a number of ways:
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*
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* (1) The NFC HAL tells us the maximum clock period the sample delay
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* DLL can tolerate. If the clock period is greater than half that
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* maximum, we must configure the DLL to be driven by half periods.
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*
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* (2) We need to convert from an ideal sample delay, in ns, to a
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* "sample delay factor," which the NFC uses. This factor depends on
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* whether we're driving the DLL with full or half periods.
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* Paraphrasing the reference manual:
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*
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* AD = SDF x 0.125 x RP
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*
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* where:
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*
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* AD is the applied delay, in ns.
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* SDF is the sample delay factor, which is dimensionless.
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* RP is the reference period, in ns, which is a full clock period
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* if the DLL is being driven by full periods, or half that if
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* the DLL is being driven by half periods.
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*
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* Let's re-arrange this in a way that's more useful to us:
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*
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* 8
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* SDF = AD x ----
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* RP
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*
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* The reference period is either the clock period or half that, so this
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* is:
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*
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* 8 AD x DDF
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* SDF = AD x ----- = --------
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* f x P P
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*
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* where:
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*
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* f is 1 or 1/2, depending on how we're driving the DLL.
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* P is the clock period.
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* DDF is the DLL Delay Factor, a dimensionless value that
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* incorporates all the constants in the conversion.
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*
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* DDF will be either 8 or 16, both of which are powers of two. We can
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* reduce the cost of this conversion by using bit shifts instead of
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* multiplication or division. Thus:
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*
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* AD << DDS
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* SDF = ---------
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* P
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*
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* or
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*
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* AD = (SDF >> DDS) x P
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*
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* where:
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*
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* DDS is the DLL Delay Shift, the logarithm to base 2 of the DDF.
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*/
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if (clock_period_in_ns > (nfc->max_dll_clock_period_in_ns >> 1)) {
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dll_use_half_periods = true;
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dll_delay_shift = 3 + 1;
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} else {
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dll_use_half_periods = false;
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dll_delay_shift = 3;
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}
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/*
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* Compute the maximum sample delay the NFC allows, under current
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* conditions. If the clock is running too slowly, no sample delay is
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* possible.
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*/
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if (clock_period_in_ns > nfc->max_dll_clock_period_in_ns)
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max_sample_delay_in_ns = 0;
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else {
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/*
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* Compute the delay implied by the largest sample delay factor
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* the NFC allows.
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*/
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max_sample_delay_in_ns =
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(nfc->max_sample_delay_factor * clock_period_in_ns) >>
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dll_delay_shift;
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/*
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* Check if the implied sample delay larger than the NFC
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* actually allows.
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*/
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if (max_sample_delay_in_ns > nfc->max_dll_delay_in_ns)
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max_sample_delay_in_ns = nfc->max_dll_delay_in_ns;
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}
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/*
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* Check if improved timing information is available. If not, we have to
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* use a less-sophisticated algorithm.
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*/
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if (!improved_timing_is_available) {
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/*
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* Fold the read setup time required by the NFC into the ideal
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* sample delay.
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*/
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ideal_sample_delay_in_ns = target.gpmi_sample_delay_in_ns +
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nfc->internal_data_setup_in_ns;
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/*
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* The ideal sample delay may be greater than the maximum
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* allowed by the NFC. If so, we can trade off sample delay time
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* for more data setup time.
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*
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* In each iteration of the following loop, we add a cycle to
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* the data setup time and subtract a corresponding amount from
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* the sample delay until we've satisified the constraints or
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* can't do any better.
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*/
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while ((ideal_sample_delay_in_ns > max_sample_delay_in_ns) &&
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|
(data_setup_in_cycles < nfc->max_data_setup_cycles)) {
|
|
|
|
data_setup_in_cycles++;
|
|
ideal_sample_delay_in_ns -= clock_period_in_ns;
|
|
|
|
if (ideal_sample_delay_in_ns < 0)
|
|
ideal_sample_delay_in_ns = 0;
|
|
|
|
}
|
|
|
|
/*
|
|
* Compute the sample delay factor that corresponds most closely
|
|
* to the ideal sample delay. If the result is too large for the
|
|
* NFC, use the maximum value.
|
|
*
|
|
* Notice that we use the ns_to_cycles function to compute the
|
|
* sample delay factor. We do this because the form of the
|
|
* computation is the same as that for calculating cycles.
|
|
*/
|
|
sample_delay_factor =
|
|
ns_to_cycles(
|
|
ideal_sample_delay_in_ns << dll_delay_shift,
|
|
clock_period_in_ns, 0);
|
|
|
|
if (sample_delay_factor > nfc->max_sample_delay_factor)
|
|
sample_delay_factor = nfc->max_sample_delay_factor;
|
|
|
|
/* Skip to the part where we return our results. */
|
|
goto return_results;
|
|
}
|
|
|
|
/*
|
|
* If control arrives here, we have more detailed timing information,
|
|
* so we can use a better algorithm.
|
|
*/
|
|
|
|
/*
|
|
* Fold the read setup time required by the NFC into the maximum
|
|
* propagation delay.
|
|
*/
|
|
max_prop_delay_in_ns += nfc->internal_data_setup_in_ns;
|
|
|
|
/*
|
|
* Earlier, we computed the number of clock cycles required to satisfy
|
|
* the data setup time. Now, we need to know the actual nanoseconds.
|
|
*/
|
|
data_setup_in_ns = clock_period_in_ns * data_setup_in_cycles;
|
|
|
|
/*
|
|
* Compute tEYE, the width of the data eye when reading from the NAND
|
|
* Flash. The eye width is fundamentally determined by the data setup
|
|
* time, perturbed by propagation delays and some characteristics of the
|
|
* NAND Flash device.
|
|
*
|
|
* start of the eye = max_prop_delay + tREA
|
|
* end of the eye = min_prop_delay + tRHOH + data_setup
|
|
*/
|
|
tEYE = (int)min_prop_delay_in_ns + (int)target.tRHOH_in_ns +
|
|
(int)data_setup_in_ns;
|
|
|
|
tEYE -= (int)max_prop_delay_in_ns + (int)target.tREA_in_ns;
|
|
|
|
/*
|
|
* The eye must be open. If it's not, we can try to open it by
|
|
* increasing its main forcer, the data setup time.
|
|
*
|
|
* In each iteration of the following loop, we increase the data setup
|
|
* time by a single clock cycle. We do this until either the eye is
|
|
* open or we run into NFC limits.
|
|
*/
|
|
while ((tEYE <= 0) &&
|
|
(data_setup_in_cycles < nfc->max_data_setup_cycles)) {
|
|
/* Give a cycle to data setup. */
|
|
data_setup_in_cycles++;
|
|
/* Synchronize the data setup time with the cycles. */
|
|
data_setup_in_ns += clock_period_in_ns;
|
|
/* Adjust tEYE accordingly. */
|
|
tEYE += clock_period_in_ns;
|
|
}
|
|
|
|
/*
|
|
* When control arrives here, the eye is open. The ideal time to sample
|
|
* the data is in the center of the eye:
|
|
*
|
|
* end of the eye + start of the eye
|
|
* --------------------------------- - data_setup
|
|
* 2
|
|
*
|
|
* After some algebra, this simplifies to the code immediately below.
|
|
*/
|
|
ideal_sample_delay_in_ns =
|
|
((int)max_prop_delay_in_ns +
|
|
(int)target.tREA_in_ns +
|
|
(int)min_prop_delay_in_ns +
|
|
(int)target.tRHOH_in_ns -
|
|
(int)data_setup_in_ns) >> 1;
|
|
|
|
/*
|
|
* The following figure illustrates some aspects of a NAND Flash read:
|
|
*
|
|
*
|
|
* __ _____________________________________
|
|
* RDN \_________________/
|
|
*
|
|
* <---- tEYE ----->
|
|
* /-----------------\
|
|
* Read Data ----------------------------< >---------
|
|
* \-----------------/
|
|
* ^ ^ ^ ^
|
|
* | | | |
|
|
* |<--Data Setup -->|<--Delay Time -->| |
|
|
* | | | |
|
|
* | | |
|
|
* | |<-- Quantized Delay Time -->|
|
|
* | | |
|
|
*
|
|
*
|
|
* We have some issues we must now address:
|
|
*
|
|
* (1) The *ideal* sample delay time must not be negative. If it is, we
|
|
* jam it to zero.
|
|
*
|
|
* (2) The *ideal* sample delay time must not be greater than that
|
|
* allowed by the NFC. If it is, we can increase the data setup
|
|
* time, which will reduce the delay between the end of the data
|
|
* setup and the center of the eye. It will also make the eye
|
|
* larger, which might help with the next issue...
|
|
*
|
|
* (3) The *quantized* sample delay time must not fall either before the
|
|
* eye opens or after it closes (the latter is the problem
|
|
* illustrated in the above figure).
|
|
*/
|
|
|
|
/* Jam a negative ideal sample delay to zero. */
|
|
if (ideal_sample_delay_in_ns < 0)
|
|
ideal_sample_delay_in_ns = 0;
|
|
|
|
/*
|
|
* Extend the data setup as needed to reduce the ideal sample delay
|
|
* below the maximum permitted by the NFC.
|
|
*/
|
|
while ((ideal_sample_delay_in_ns > max_sample_delay_in_ns) &&
|
|
(data_setup_in_cycles < nfc->max_data_setup_cycles)) {
|
|
|
|
/* Give a cycle to data setup. */
|
|
data_setup_in_cycles++;
|
|
/* Synchronize the data setup time with the cycles. */
|
|
data_setup_in_ns += clock_period_in_ns;
|
|
/* Adjust tEYE accordingly. */
|
|
tEYE += clock_period_in_ns;
|
|
|
|
/*
|
|
* Decrease the ideal sample delay by one half cycle, to keep it
|
|
* in the middle of the eye.
|
|
*/
|
|
ideal_sample_delay_in_ns -= (clock_period_in_ns >> 1);
|
|
|
|
/* Jam a negative ideal sample delay to zero. */
|
|
if (ideal_sample_delay_in_ns < 0)
|
|
ideal_sample_delay_in_ns = 0;
|
|
}
|
|
|
|
/*
|
|
* Compute the sample delay factor that corresponds to the ideal sample
|
|
* delay. If the result is too large, then use the maximum allowed
|
|
* value.
|
|
*
|
|
* Notice that we use the ns_to_cycles function to compute the sample
|
|
* delay factor. We do this because the form of the computation is the
|
|
* same as that for calculating cycles.
|
|
*/
|
|
sample_delay_factor =
|
|
ns_to_cycles(ideal_sample_delay_in_ns << dll_delay_shift,
|
|
clock_period_in_ns, 0);
|
|
|
|
if (sample_delay_factor > nfc->max_sample_delay_factor)
|
|
sample_delay_factor = nfc->max_sample_delay_factor;
|
|
|
|
/*
|
|
* These macros conveniently encapsulate a computation we'll use to
|
|
* continuously evaluate whether or not the data sample delay is inside
|
|
* the eye.
|
|
*/
|
|
#define IDEAL_DELAY ((int) ideal_sample_delay_in_ns)
|
|
|
|
#define QUANTIZED_DELAY \
|
|
((int) ((sample_delay_factor * clock_period_in_ns) >> \
|
|
dll_delay_shift))
|
|
|
|
#define DELAY_ERROR (abs(QUANTIZED_DELAY - IDEAL_DELAY))
|
|
|
|
#define SAMPLE_IS_NOT_WITHIN_THE_EYE (DELAY_ERROR > (tEYE >> 1))
|
|
|
|
/*
|
|
* While the quantized sample time falls outside the eye, reduce the
|
|
* sample delay or extend the data setup to move the sampling point back
|
|
* toward the eye. Do not allow the number of data setup cycles to
|
|
* exceed the maximum allowed by the NFC.
|
|
*/
|
|
while (SAMPLE_IS_NOT_WITHIN_THE_EYE &&
|
|
(data_setup_in_cycles < nfc->max_data_setup_cycles)) {
|
|
/*
|
|
* If control arrives here, the quantized sample delay falls
|
|
* outside the eye. Check if it's before the eye opens, or after
|
|
* the eye closes.
|
|
*/
|
|
if (QUANTIZED_DELAY > IDEAL_DELAY) {
|
|
/*
|
|
* If control arrives here, the quantized sample delay
|
|
* falls after the eye closes. Decrease the quantized
|
|
* delay time and then go back to re-evaluate.
|
|
*/
|
|
if (sample_delay_factor != 0)
|
|
sample_delay_factor--;
|
|
continue;
|
|
}
|
|
|
|
/*
|
|
* If control arrives here, the quantized sample delay falls
|
|
* before the eye opens. Shift the sample point by increasing
|
|
* data setup time. This will also make the eye larger.
|
|
*/
|
|
|
|
/* Give a cycle to data setup. */
|
|
data_setup_in_cycles++;
|
|
/* Synchronize the data setup time with the cycles. */
|
|
data_setup_in_ns += clock_period_in_ns;
|
|
/* Adjust tEYE accordingly. */
|
|
tEYE += clock_period_in_ns;
|
|
|
|
/*
|
|
* Decrease the ideal sample delay by one half cycle, to keep it
|
|
* in the middle of the eye.
|
|
*/
|
|
ideal_sample_delay_in_ns -= (clock_period_in_ns >> 1);
|
|
|
|
/* ...and one less period for the delay time. */
|
|
ideal_sample_delay_in_ns -= clock_period_in_ns;
|
|
|
|
/* Jam a negative ideal sample delay to zero. */
|
|
if (ideal_sample_delay_in_ns < 0)
|
|
ideal_sample_delay_in_ns = 0;
|
|
|
|
/*
|
|
* We have a new ideal sample delay, so re-compute the quantized
|
|
* delay.
|
|
*/
|
|
sample_delay_factor =
|
|
ns_to_cycles(
|
|
ideal_sample_delay_in_ns << dll_delay_shift,
|
|
clock_period_in_ns, 0);
|
|
|
|
if (sample_delay_factor > nfc->max_sample_delay_factor)
|
|
sample_delay_factor = nfc->max_sample_delay_factor;
|
|
}
|
|
|
|
/* Control arrives here when we're ready to return our results. */
|
|
return_results:
|
|
hw->data_setup_in_cycles = data_setup_in_cycles;
|
|
hw->data_hold_in_cycles = data_hold_in_cycles;
|
|
hw->address_setup_in_cycles = address_setup_in_cycles;
|
|
hw->use_half_periods = dll_use_half_periods;
|
|
hw->sample_delay_factor = sample_delay_factor;
|
|
hw->device_busy_timeout = GPMI_DEFAULT_BUSY_TIMEOUT;
|
|
hw->wrn_dly_sel = BV_GPMI_CTRL1_WRN_DLY_SEL_4_TO_8NS;
|
|
|
|
/* Return success. */
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* <1> Firstly, we should know what's the GPMI-clock means.
|
|
* The GPMI-clock is the internal clock in the gpmi nand controller.
|
|
* If you set 100MHz to gpmi nand controller, the GPMI-clock's period
|
|
* is 10ns. Mark the GPMI-clock's period as GPMI-clock-period.
|
|
*
|
|
* <2> Secondly, we should know what's the frequency on the nand chip pins.
|
|
* The frequency on the nand chip pins is derived from the GPMI-clock.
|
|
* We can get it from the following equation:
|
|
*
|
|
* F = G / (DS + DH)
|
|
*
|
|
* F : the frequency on the nand chip pins.
|
|
* G : the GPMI clock, such as 100MHz.
|
|
* DS : GPMI_HW_GPMI_TIMING0:DATA_SETUP
|
|
* DH : GPMI_HW_GPMI_TIMING0:DATA_HOLD
|
|
*
|
|
* <3> Thirdly, when the frequency on the nand chip pins is above 33MHz,
|
|
* the nand EDO(extended Data Out) timing could be applied.
|
|
* The GPMI implements a feedback read strobe to sample the read data.
|
|
* The feedback read strobe can be delayed to support the nand EDO timing
|
|
* where the read strobe may deasserts before the read data is valid, and
|
|
* read data is valid for some time after read strobe.
|
|
*
|
|
* The following figure illustrates some aspects of a NAND Flash read:
|
|
*
|
|
* |<---tREA---->|
|
|
* | |
|
|
* | | |
|
|
* |<--tRP-->| |
|
|
* | | |
|
|
* __ ___|__________________________________
|
|
* RDN \________/ |
|
|
* |
|
|
* /---------\
|
|
* Read Data --------------< >---------
|
|
* \---------/
|
|
* | |
|
|
* |<-D->|
|
|
* FeedbackRDN ________ ____________
|
|
* \___________/
|
|
*
|
|
* D stands for delay, set in the HW_GPMI_CTRL1:RDN_DELAY.
|
|
*
|
|
*
|
|
* <4> Now, we begin to describe how to compute the right RDN_DELAY.
|
|
*
|
|
* 4.1) From the aspect of the nand chip pins:
|
|
* Delay = (tREA + C - tRP) {1}
|
|
*
|
|
* tREA : the maximum read access time. From the ONFI nand standards,
|
|
* we know that tREA is 16ns in mode 5, tREA is 20ns is mode 4.
|
|
* Please check it in : www.onfi.org
|
|
* C : a constant for adjust the delay. default is 4.
|
|
* tRP : the read pulse width.
|
|
* Specified by the HW_GPMI_TIMING0:DATA_SETUP:
|
|
* tRP = (GPMI-clock-period) * DATA_SETUP
|
|
*
|
|
* 4.2) From the aspect of the GPMI nand controller:
|
|
* Delay = RDN_DELAY * 0.125 * RP {2}
|
|
*
|
|
* RP : the DLL reference period.
|
|
* if (GPMI-clock-period > DLL_THRETHOLD)
|
|
* RP = GPMI-clock-period / 2;
|
|
* else
|
|
* RP = GPMI-clock-period;
|
|
*
|
|
* Set the HW_GPMI_CTRL1:HALF_PERIOD if GPMI-clock-period
|
|
* is greater DLL_THRETHOLD. In other SOCs, the DLL_THRETHOLD
|
|
* is 16ns, but in mx6q, we use 12ns.
|
|
*
|
|
* 4.3) since {1} equals {2}, we get:
|
|
*
|
|
* (tREA + 4 - tRP) * 8
|
|
* RDN_DELAY = --------------------- {3}
|
|
* RP
|
|
*
|
|
* 4.4) We only support the fastest asynchronous mode of ONFI nand.
|
|
* For some ONFI nand, the mode 4 is the fastest mode;
|
|
* while for some ONFI nand, the mode 5 is the fastest mode.
|
|
* So we only support the mode 4 and mode 5. It is no need to
|
|
* support other modes.
|
|
*/
|
|
static void gpmi_compute_edo_timing(struct gpmi_nand_data *this,
|
|
struct gpmi_nfc_hardware_timing *hw)
|
|
{
|
|
struct resources *r = &this->resources;
|
|
unsigned long rate = clk_get_rate(r->clock[0]);
|
|
int mode = this->timing_mode;
|
|
int dll_threshold = 16; /* in ns */
|
|
unsigned long delay;
|
|
unsigned long clk_period;
|
|
int t_rea;
|
|
int c = 4;
|
|
int t_rp;
|
|
int rp;
|
|
|
|
/*
|
|
* [1] for GPMI_HW_GPMI_TIMING0:
|
|
* The async mode requires 40MHz for mode 4, 50MHz for mode 5.
|
|
* The GPMI can support 100MHz at most. So if we want to
|
|
* get the 40MHz or 50MHz, we have to set DS=1, DH=1.
|
|
* Set the ADDRESS_SETUP to 0 in mode 4.
|
|
*/
|
|
hw->data_setup_in_cycles = 1;
|
|
hw->data_hold_in_cycles = 1;
|
|
hw->address_setup_in_cycles = ((mode == 5) ? 1 : 0);
|
|
|
|
/* [2] for GPMI_HW_GPMI_TIMING1 */
|
|
hw->device_busy_timeout = 0x9000;
|
|
|
|
/* [3] for GPMI_HW_GPMI_CTRL1 */
|
|
hw->wrn_dly_sel = BV_GPMI_CTRL1_WRN_DLY_SEL_NO_DELAY;
|
|
|
|
if (GPMI_IS_MX6Q(this))
|
|
dll_threshold = 12;
|
|
|
|
/*
|
|
* Enlarge 10 times for the numerator and denominator in {3}.
|
|
* This make us to get more accurate result.
|
|
*/
|
|
clk_period = NSEC_PER_SEC / (rate / 10);
|
|
dll_threshold *= 10;
|
|
t_rea = ((mode == 5) ? 16 : 20) * 10;
|
|
c *= 10;
|
|
|
|
t_rp = clk_period * 1; /* DATA_SETUP is 1 */
|
|
|
|
if (clk_period > dll_threshold) {
|
|
hw->use_half_periods = 1;
|
|
rp = clk_period / 2;
|
|
} else {
|
|
hw->use_half_periods = 0;
|
|
rp = clk_period;
|
|
}
|
|
|
|
/*
|
|
* Multiply the numerator with 10, we could do a round off:
|
|
* 7.8 round up to 8; 7.4 round down to 7.
|
|
*/
|
|
delay = (((t_rea + c - t_rp) * 8) * 10) / rp;
|
|
delay = (delay + 5) / 10;
|
|
|
|
hw->sample_delay_factor = delay;
|
|
}
|
|
|
|
static int enable_edo_mode(struct gpmi_nand_data *this, int mode)
|
|
{
|
|
struct resources *r = &this->resources;
|
|
struct nand_chip *nand = &this->nand;
|
|
struct mtd_info *mtd = &this->mtd;
|
|
uint8_t feature[ONFI_SUBFEATURE_PARAM_LEN] = {};
|
|
unsigned long rate;
|
|
int ret;
|
|
|
|
nand->select_chip(mtd, 0);
|
|
|
|
/* [1] send SET FEATURE commond to NAND */
|
|
feature[0] = mode;
|
|
ret = nand->onfi_set_features(mtd, nand,
|
|
ONFI_FEATURE_ADDR_TIMING_MODE, feature);
|
|
if (ret)
|
|
goto err_out;
|
|
|
|
/* [2] send GET FEATURE command to double-check the timing mode */
|
|
memset(feature, 0, ONFI_SUBFEATURE_PARAM_LEN);
|
|
ret = nand->onfi_get_features(mtd, nand,
|
|
ONFI_FEATURE_ADDR_TIMING_MODE, feature);
|
|
if (ret || feature[0] != mode)
|
|
goto err_out;
|
|
|
|
nand->select_chip(mtd, -1);
|
|
|
|
/* [3] set the main IO clock, 100MHz for mode 5, 80MHz for mode 4. */
|
|
rate = (mode == 5) ? 100000000 : 80000000;
|
|
clk_set_rate(r->clock[0], rate);
|
|
|
|
/* Let the gpmi_begin() re-compute the timing again. */
|
|
this->flags &= ~GPMI_TIMING_INIT_OK;
|
|
|
|
this->flags |= GPMI_ASYNC_EDO_ENABLED;
|
|
this->timing_mode = mode;
|
|
dev_info(this->dev, "enable the asynchronous EDO mode %d\n", mode);
|
|
return 0;
|
|
|
|
err_out:
|
|
nand->select_chip(mtd, -1);
|
|
dev_err(this->dev, "mode:%d ,failed in set feature.\n", mode);
|
|
return -EINVAL;
|
|
}
|
|
|
|
int gpmi_extra_init(struct gpmi_nand_data *this)
|
|
{
|
|
struct nand_chip *chip = &this->nand;
|
|
|
|
/* Enable the asynchronous EDO feature. */
|
|
if (GPMI_IS_MX6Q(this) && chip->onfi_version) {
|
|
int mode = onfi_get_async_timing_mode(chip);
|
|
|
|
/* We only support the timing mode 4 and mode 5. */
|
|
if (mode & ONFI_TIMING_MODE_5)
|
|
mode = 5;
|
|
else if (mode & ONFI_TIMING_MODE_4)
|
|
mode = 4;
|
|
else
|
|
return 0;
|
|
|
|
return enable_edo_mode(this, mode);
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
/* Begin the I/O */
|
|
void gpmi_begin(struct gpmi_nand_data *this)
|
|
{
|
|
struct resources *r = &this->resources;
|
|
void __iomem *gpmi_regs = r->gpmi_regs;
|
|
unsigned int clock_period_in_ns;
|
|
uint32_t reg;
|
|
unsigned int dll_wait_time_in_us;
|
|
struct gpmi_nfc_hardware_timing hw;
|
|
int ret;
|
|
|
|
/* Enable the clock. */
|
|
ret = gpmi_enable_clk(this);
|
|
if (ret) {
|
|
pr_err("We failed in enable the clk\n");
|
|
goto err_out;
|
|
}
|
|
|
|
/* Only initialize the timing once */
|
|
if (this->flags & GPMI_TIMING_INIT_OK)
|
|
return;
|
|
this->flags |= GPMI_TIMING_INIT_OK;
|
|
|
|
if (this->flags & GPMI_ASYNC_EDO_ENABLED)
|
|
gpmi_compute_edo_timing(this, &hw);
|
|
else
|
|
gpmi_nfc_compute_hardware_timing(this, &hw);
|
|
|
|
/* [1] Set HW_GPMI_TIMING0 */
|
|
reg = BF_GPMI_TIMING0_ADDRESS_SETUP(hw.address_setup_in_cycles) |
|
|
BF_GPMI_TIMING0_DATA_HOLD(hw.data_hold_in_cycles) |
|
|
BF_GPMI_TIMING0_DATA_SETUP(hw.data_setup_in_cycles) ;
|
|
|
|
writel(reg, gpmi_regs + HW_GPMI_TIMING0);
|
|
|
|
/* [2] Set HW_GPMI_TIMING1 */
|
|
writel(BF_GPMI_TIMING1_BUSY_TIMEOUT(hw.device_busy_timeout),
|
|
gpmi_regs + HW_GPMI_TIMING1);
|
|
|
|
/* [3] The following code is to set the HW_GPMI_CTRL1. */
|
|
|
|
/* Set the WRN_DLY_SEL */
|
|
writel(BM_GPMI_CTRL1_WRN_DLY_SEL, gpmi_regs + HW_GPMI_CTRL1_CLR);
|
|
writel(BF_GPMI_CTRL1_WRN_DLY_SEL(hw.wrn_dly_sel),
|
|
gpmi_regs + HW_GPMI_CTRL1_SET);
|
|
|
|
/* DLL_ENABLE must be set to 0 when setting RDN_DELAY or HALF_PERIOD. */
|
|
writel(BM_GPMI_CTRL1_DLL_ENABLE, gpmi_regs + HW_GPMI_CTRL1_CLR);
|
|
|
|
/* Clear out the DLL control fields. */
|
|
reg = BM_GPMI_CTRL1_RDN_DELAY | BM_GPMI_CTRL1_HALF_PERIOD;
|
|
writel(reg, gpmi_regs + HW_GPMI_CTRL1_CLR);
|
|
|
|
/* If no sample delay is called for, return immediately. */
|
|
if (!hw.sample_delay_factor)
|
|
return;
|
|
|
|
/* Set RDN_DELAY or HALF_PERIOD. */
|
|
reg = ((hw.use_half_periods) ? BM_GPMI_CTRL1_HALF_PERIOD : 0)
|
|
| BF_GPMI_CTRL1_RDN_DELAY(hw.sample_delay_factor);
|
|
|
|
writel(reg, gpmi_regs + HW_GPMI_CTRL1_SET);
|
|
|
|
/* At last, we enable the DLL. */
|
|
writel(BM_GPMI_CTRL1_DLL_ENABLE, gpmi_regs + HW_GPMI_CTRL1_SET);
|
|
|
|
/*
|
|
* After we enable the GPMI DLL, we have to wait 64 clock cycles before
|
|
* we can use the GPMI. Calculate the amount of time we need to wait,
|
|
* in microseconds.
|
|
*/
|
|
clock_period_in_ns = NSEC_PER_SEC / clk_get_rate(r->clock[0]);
|
|
dll_wait_time_in_us = (clock_period_in_ns * 64) / 1000;
|
|
|
|
if (!dll_wait_time_in_us)
|
|
dll_wait_time_in_us = 1;
|
|
|
|
/* Wait for the DLL to settle. */
|
|
udelay(dll_wait_time_in_us);
|
|
|
|
err_out:
|
|
return;
|
|
}
|
|
|
|
void gpmi_end(struct gpmi_nand_data *this)
|
|
{
|
|
gpmi_disable_clk(this);
|
|
}
|
|
|
|
/* Clears a BCH interrupt. */
|
|
void gpmi_clear_bch(struct gpmi_nand_data *this)
|
|
{
|
|
struct resources *r = &this->resources;
|
|
writel(BM_BCH_CTRL_COMPLETE_IRQ, r->bch_regs + HW_BCH_CTRL_CLR);
|
|
}
|
|
|
|
/* Returns the Ready/Busy status of the given chip. */
|
|
int gpmi_is_ready(struct gpmi_nand_data *this, unsigned chip)
|
|
{
|
|
struct resources *r = &this->resources;
|
|
uint32_t mask = 0;
|
|
uint32_t reg = 0;
|
|
|
|
if (GPMI_IS_MX23(this)) {
|
|
mask = MX23_BM_GPMI_DEBUG_READY0 << chip;
|
|
reg = readl(r->gpmi_regs + HW_GPMI_DEBUG);
|
|
} else if (GPMI_IS_MX28(this) || GPMI_IS_MX6Q(this)) {
|
|
/* MX28 shares the same R/B register as MX6Q. */
|
|
mask = MX28_BF_GPMI_STAT_READY_BUSY(1 << chip);
|
|
reg = readl(r->gpmi_regs + HW_GPMI_STAT);
|
|
} else
|
|
pr_err("unknow arch.\n");
|
|
return reg & mask;
|
|
}
|
|
|
|
static inline void set_dma_type(struct gpmi_nand_data *this,
|
|
enum dma_ops_type type)
|
|
{
|
|
this->last_dma_type = this->dma_type;
|
|
this->dma_type = type;
|
|
}
|
|
|
|
int gpmi_send_command(struct gpmi_nand_data *this)
|
|
{
|
|
struct dma_chan *channel = get_dma_chan(this);
|
|
struct dma_async_tx_descriptor *desc;
|
|
struct scatterlist *sgl;
|
|
int chip = this->current_chip;
|
|
u32 pio[3];
|
|
|
|
/* [1] send out the PIO words */
|
|
pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(BV_GPMI_CTRL0_COMMAND_MODE__WRITE)
|
|
| BM_GPMI_CTRL0_WORD_LENGTH
|
|
| BF_GPMI_CTRL0_CS(chip, this)
|
|
| BF_GPMI_CTRL0_LOCK_CS(LOCK_CS_ENABLE, this)
|
|
| BF_GPMI_CTRL0_ADDRESS(BV_GPMI_CTRL0_ADDRESS__NAND_CLE)
|
|
| BM_GPMI_CTRL0_ADDRESS_INCREMENT
|
|
| BF_GPMI_CTRL0_XFER_COUNT(this->command_length);
|
|
pio[1] = pio[2] = 0;
|
|
desc = dmaengine_prep_slave_sg(channel,
|
|
(struct scatterlist *)pio,
|
|
ARRAY_SIZE(pio), DMA_TRANS_NONE, 0);
|
|
if (!desc) {
|
|
pr_err("step 1 error\n");
|
|
return -1;
|
|
}
|
|
|
|
/* [2] send out the COMMAND + ADDRESS string stored in @buffer */
|
|
sgl = &this->cmd_sgl;
|
|
|
|
sg_init_one(sgl, this->cmd_buffer, this->command_length);
|
|
dma_map_sg(this->dev, sgl, 1, DMA_TO_DEVICE);
|
|
desc = dmaengine_prep_slave_sg(channel,
|
|
sgl, 1, DMA_MEM_TO_DEV,
|
|
DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
|
|
|
|
if (!desc) {
|
|
pr_err("step 2 error\n");
|
|
return -1;
|
|
}
|
|
|
|
/* [3] submit the DMA */
|
|
set_dma_type(this, DMA_FOR_COMMAND);
|
|
return start_dma_without_bch_irq(this, desc);
|
|
}
|
|
|
|
int gpmi_send_data(struct gpmi_nand_data *this)
|
|
{
|
|
struct dma_async_tx_descriptor *desc;
|
|
struct dma_chan *channel = get_dma_chan(this);
|
|
int chip = this->current_chip;
|
|
uint32_t command_mode;
|
|
uint32_t address;
|
|
u32 pio[2];
|
|
|
|
/* [1] PIO */
|
|
command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WRITE;
|
|
address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
|
|
|
|
pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(command_mode)
|
|
| BM_GPMI_CTRL0_WORD_LENGTH
|
|
| BF_GPMI_CTRL0_CS(chip, this)
|
|
| BF_GPMI_CTRL0_LOCK_CS(LOCK_CS_ENABLE, this)
|
|
| BF_GPMI_CTRL0_ADDRESS(address)
|
|
| BF_GPMI_CTRL0_XFER_COUNT(this->upper_len);
|
|
pio[1] = 0;
|
|
desc = dmaengine_prep_slave_sg(channel, (struct scatterlist *)pio,
|
|
ARRAY_SIZE(pio), DMA_TRANS_NONE, 0);
|
|
if (!desc) {
|
|
pr_err("step 1 error\n");
|
|
return -1;
|
|
}
|
|
|
|
/* [2] send DMA request */
|
|
prepare_data_dma(this, DMA_TO_DEVICE);
|
|
desc = dmaengine_prep_slave_sg(channel, &this->data_sgl,
|
|
1, DMA_MEM_TO_DEV,
|
|
DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
|
|
if (!desc) {
|
|
pr_err("step 2 error\n");
|
|
return -1;
|
|
}
|
|
/* [3] submit the DMA */
|
|
set_dma_type(this, DMA_FOR_WRITE_DATA);
|
|
return start_dma_without_bch_irq(this, desc);
|
|
}
|
|
|
|
int gpmi_read_data(struct gpmi_nand_data *this)
|
|
{
|
|
struct dma_async_tx_descriptor *desc;
|
|
struct dma_chan *channel = get_dma_chan(this);
|
|
int chip = this->current_chip;
|
|
u32 pio[2];
|
|
|
|
/* [1] : send PIO */
|
|
pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(BV_GPMI_CTRL0_COMMAND_MODE__READ)
|
|
| BM_GPMI_CTRL0_WORD_LENGTH
|
|
| BF_GPMI_CTRL0_CS(chip, this)
|
|
| BF_GPMI_CTRL0_LOCK_CS(LOCK_CS_ENABLE, this)
|
|
| BF_GPMI_CTRL0_ADDRESS(BV_GPMI_CTRL0_ADDRESS__NAND_DATA)
|
|
| BF_GPMI_CTRL0_XFER_COUNT(this->upper_len);
|
|
pio[1] = 0;
|
|
desc = dmaengine_prep_slave_sg(channel,
|
|
(struct scatterlist *)pio,
|
|
ARRAY_SIZE(pio), DMA_TRANS_NONE, 0);
|
|
if (!desc) {
|
|
pr_err("step 1 error\n");
|
|
return -1;
|
|
}
|
|
|
|
/* [2] : send DMA request */
|
|
prepare_data_dma(this, DMA_FROM_DEVICE);
|
|
desc = dmaengine_prep_slave_sg(channel, &this->data_sgl,
|
|
1, DMA_DEV_TO_MEM,
|
|
DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
|
|
if (!desc) {
|
|
pr_err("step 2 error\n");
|
|
return -1;
|
|
}
|
|
|
|
/* [3] : submit the DMA */
|
|
set_dma_type(this, DMA_FOR_READ_DATA);
|
|
return start_dma_without_bch_irq(this, desc);
|
|
}
|
|
|
|
int gpmi_send_page(struct gpmi_nand_data *this,
|
|
dma_addr_t payload, dma_addr_t auxiliary)
|
|
{
|
|
struct bch_geometry *geo = &this->bch_geometry;
|
|
uint32_t command_mode;
|
|
uint32_t address;
|
|
uint32_t ecc_command;
|
|
uint32_t buffer_mask;
|
|
struct dma_async_tx_descriptor *desc;
|
|
struct dma_chan *channel = get_dma_chan(this);
|
|
int chip = this->current_chip;
|
|
u32 pio[6];
|
|
|
|
/* A DMA descriptor that does an ECC page read. */
|
|
command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WRITE;
|
|
address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
|
|
ecc_command = BV_GPMI_ECCCTRL_ECC_CMD__BCH_ENCODE;
|
|
buffer_mask = BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_PAGE |
|
|
BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_AUXONLY;
|
|
|
|
pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(command_mode)
|
|
| BM_GPMI_CTRL0_WORD_LENGTH
|
|
| BF_GPMI_CTRL0_CS(chip, this)
|
|
| BF_GPMI_CTRL0_LOCK_CS(LOCK_CS_ENABLE, this)
|
|
| BF_GPMI_CTRL0_ADDRESS(address)
|
|
| BF_GPMI_CTRL0_XFER_COUNT(0);
|
|
pio[1] = 0;
|
|
pio[2] = BM_GPMI_ECCCTRL_ENABLE_ECC
|
|
| BF_GPMI_ECCCTRL_ECC_CMD(ecc_command)
|
|
| BF_GPMI_ECCCTRL_BUFFER_MASK(buffer_mask);
|
|
pio[3] = geo->page_size;
|
|
pio[4] = payload;
|
|
pio[5] = auxiliary;
|
|
|
|
desc = dmaengine_prep_slave_sg(channel,
|
|
(struct scatterlist *)pio,
|
|
ARRAY_SIZE(pio), DMA_TRANS_NONE,
|
|
DMA_CTRL_ACK);
|
|
if (!desc) {
|
|
pr_err("step 2 error\n");
|
|
return -1;
|
|
}
|
|
set_dma_type(this, DMA_FOR_WRITE_ECC_PAGE);
|
|
return start_dma_with_bch_irq(this, desc);
|
|
}
|
|
|
|
int gpmi_read_page(struct gpmi_nand_data *this,
|
|
dma_addr_t payload, dma_addr_t auxiliary)
|
|
{
|
|
struct bch_geometry *geo = &this->bch_geometry;
|
|
uint32_t command_mode;
|
|
uint32_t address;
|
|
uint32_t ecc_command;
|
|
uint32_t buffer_mask;
|
|
struct dma_async_tx_descriptor *desc;
|
|
struct dma_chan *channel = get_dma_chan(this);
|
|
int chip = this->current_chip;
|
|
u32 pio[6];
|
|
|
|
/* [1] Wait for the chip to report ready. */
|
|
command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY;
|
|
address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
|
|
|
|
pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(command_mode)
|
|
| BM_GPMI_CTRL0_WORD_LENGTH
|
|
| BF_GPMI_CTRL0_CS(chip, this)
|
|
| BF_GPMI_CTRL0_LOCK_CS(LOCK_CS_ENABLE, this)
|
|
| BF_GPMI_CTRL0_ADDRESS(address)
|
|
| BF_GPMI_CTRL0_XFER_COUNT(0);
|
|
pio[1] = 0;
|
|
desc = dmaengine_prep_slave_sg(channel,
|
|
(struct scatterlist *)pio, 2,
|
|
DMA_TRANS_NONE, 0);
|
|
if (!desc) {
|
|
pr_err("step 1 error\n");
|
|
return -1;
|
|
}
|
|
|
|
/* [2] Enable the BCH block and read. */
|
|
command_mode = BV_GPMI_CTRL0_COMMAND_MODE__READ;
|
|
address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
|
|
ecc_command = BV_GPMI_ECCCTRL_ECC_CMD__BCH_DECODE;
|
|
buffer_mask = BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_PAGE
|
|
| BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_AUXONLY;
|
|
|
|
pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(command_mode)
|
|
| BM_GPMI_CTRL0_WORD_LENGTH
|
|
| BF_GPMI_CTRL0_CS(chip, this)
|
|
| BF_GPMI_CTRL0_LOCK_CS(LOCK_CS_ENABLE, this)
|
|
| BF_GPMI_CTRL0_ADDRESS(address)
|
|
| BF_GPMI_CTRL0_XFER_COUNT(geo->page_size);
|
|
|
|
pio[1] = 0;
|
|
pio[2] = BM_GPMI_ECCCTRL_ENABLE_ECC
|
|
| BF_GPMI_ECCCTRL_ECC_CMD(ecc_command)
|
|
| BF_GPMI_ECCCTRL_BUFFER_MASK(buffer_mask);
|
|
pio[3] = geo->page_size;
|
|
pio[4] = payload;
|
|
pio[5] = auxiliary;
|
|
desc = dmaengine_prep_slave_sg(channel,
|
|
(struct scatterlist *)pio,
|
|
ARRAY_SIZE(pio), DMA_TRANS_NONE,
|
|
DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
|
|
if (!desc) {
|
|
pr_err("step 2 error\n");
|
|
return -1;
|
|
}
|
|
|
|
/* [3] Disable the BCH block */
|
|
command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY;
|
|
address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
|
|
|
|
pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(command_mode)
|
|
| BM_GPMI_CTRL0_WORD_LENGTH
|
|
| BF_GPMI_CTRL0_CS(chip, this)
|
|
| BF_GPMI_CTRL0_LOCK_CS(LOCK_CS_ENABLE, this)
|
|
| BF_GPMI_CTRL0_ADDRESS(address)
|
|
| BF_GPMI_CTRL0_XFER_COUNT(geo->page_size);
|
|
pio[1] = 0;
|
|
pio[2] = 0; /* clear GPMI_HW_GPMI_ECCCTRL, disable the BCH. */
|
|
desc = dmaengine_prep_slave_sg(channel,
|
|
(struct scatterlist *)pio, 3,
|
|
DMA_TRANS_NONE,
|
|
DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
|
|
if (!desc) {
|
|
pr_err("step 3 error\n");
|
|
return -1;
|
|
}
|
|
|
|
/* [4] submit the DMA */
|
|
set_dma_type(this, DMA_FOR_READ_ECC_PAGE);
|
|
return start_dma_with_bch_irq(this, desc);
|
|
}
|